PandA-2024.02
mips.c
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1 /*
2 +--------------------------------------------------------------------------+
3 | CHStone : a suite of benchmark programs for C-based High-Level Synthesis |
4 | ======================================================================== |
5 | |
6 | * Collected and Modified : Y. Hara, H. Tomiyama, S. Honda, |
7 | H. Takada and K. Ishii |
8 | Nagoya University, Japan |
9 | |
10 | * Remark : |
11 | 1. This source code is modified to unify the formats of the benchmark |
12 | programs in CHStone. |
13 | 2. Test vectors are added for CHStone. |
14 | 3. If "main_result" is 0 at the end of the program, the program is |
15 | correctly executed. |
16 | 4. Please follow the copyright of each benchmark program. |
17 +--------------------------------------------------------------------------+
18 */
19 /*
20  * Copyright (C) 2008
21  * Y. Hara, H. Tomiyama, S. Honda, H. Takada and K. Ishii
22  * Nagoya University, Japan
23  * All rights reserved.
24  *
25  * Disclaimer of Warranty
26  *
27  * These software programs are available to the user without any license fee or
28  * royalty on an "as is" basis. The authors disclaims any and all warranties,
29  * whether express, implied, or statuary, including any implied warranties or
30  * merchantability or of fitness for a particular purpose. In no event shall the
31  * copyright-holder be liable for any incidental, punitive, or consequential damages
32  * of any kind whatsoever arising from the use of these programs. This disclaimer
33  * of warranty extends to the user of these programs and user's customers, employees,
34  * agents, transferees, successors, and assigns.
35  *
36  */
37 //#define DWARV
38 #include <stdio.h>
39 #ifndef DWARV
41 #endif
42 
43 #define R 0
44 
45 #define ADDU 33
46 #define SUBU 35
47 
48 #define MULT 24
49 #define MULTU 25
50 
51 #define MFHI 16
52 #define MFLO 18
53 
54 #define AND 36
55 #define OR 37
56 #define XOR 38
57 #define SLL 0
58 #define SRL 2
59 #define SLLV 4
60 #define SRLV 6
61 
62 #define SLT 42
63 #define SLTU 43
64 
65 #define JR 8
66 
67 #define J 2
68 #define JAL 3
69 
70 #define ADDIU 9
71 #define ANDI 12
72 #define ORI 13
73 #define XORI 14
74 
75 #define LW 35
76 #define SW 43
77 #define LUI 15
78 
79 #define BEQ 4
80 #define BNE 5
81 #define BGEZ 1
82 
83 #define SLTI 10
84 #define SLTIU 11
85 
86 #include "imem.h"
87 /*
88 +--------------------------------------------------------------------------+
89 | * Test Vectors (added for CHStone) |
90 | A : input data |
91 | outData : expected output data |
92 +--------------------------------------------------------------------------+
93 */
94 
95 const int A[8] = { 22, 5, -9, 3, -17, 38, 0, 11 };
96 const int outData[8] = { -17, -9, 0, 3, 5, 11, 22, 38 };
97 
98 #define IADDR(x) (((x)&0x000000ff)>>2)
99 #define DADDR(x) (((x)&0x000000ff)>>2)
100 
101 #pragma map generate_hw
102 void
103 __attribute__ ((noinline))
104 mips_call(int reg[32], unsigned long m_imem[44], int n_inst[1], int dmem[64])
105 {
106  long long hilo;
107  int Hi;
108  int Lo;
109  int pc = 0;
110  int j;
111 
112  unsigned int ins;
113  int op;
114  int rs;
115  int rt;
116  int rd;
117  int shamt;
118  int funct;
119  short address;
120  int tgtadr;
121  extern void __builtin_bambu_time_start();
122  extern void __builtin_bambu_time_stop();
124  do
125  {
126  ins = m_imem[IADDR (pc)];
127  pc = pc + 4;
128 
129  op = ins >> 26;
130 
131  switch (op)
132  {
133  case R:
134  funct = ins & 0x3f;
135  shamt = (ins >> 6) & 0x1f;
136  rd = (ins >> 11) & 0x1f;
137  rt = (ins >> 16) & 0x1f;
138  rs = (ins >> 21) & 0x1f;
139 
140  switch (funct)
141  {
142 
143  case ADDU:
144  reg[rd] = reg[rs] + reg[rt];
145  break;
146  case SUBU:
147  reg[rd] = reg[rs] - reg[rt];
148  break;
149 
150  case MULT:
151  hilo = (long long) reg[rs] * (long long) reg[rt];
152  Lo = hilo & 0x00000000ffffffffULL;
153  Hi = ((int) (hilo >> 32)) & 0xffffffffUL;
154  break;
155  case MULTU:
156  hilo =
157  (unsigned long long) ((unsigned int) (reg[rs])) *
158  (unsigned long long) ((unsigned int) (reg[rt]));
159  Lo = hilo & 0x00000000ffffffffULL;
160  Hi = ((int) (hilo >> 32)) & 0xffffffffUL;
161  break;
162 
163  case MFHI:
164  reg[rd] = Hi;
165  break;
166  case MFLO:
167  reg[rd] = Lo;
168  break;
169 
170  case AND:
171  reg[rd] = reg[rs] & reg[rt];
172  break;
173  case OR:
174  reg[rd] = reg[rs] | reg[rt];
175  break;
176  case XOR:
177  reg[rd] = reg[rs] ^ reg[rt];
178  break;
179  case SLL:
180  reg[rd] = reg[rt] << shamt;
181  break;
182  case SRL:
183  reg[rd] = reg[rt] >> shamt;
184  break;
185  case SLLV:
186  reg[rd] = reg[rt] << reg[rs];
187  break;
188  case SRLV:
189  reg[rd] = reg[rt] >> reg[rs];
190  break;
191 
192  case SLT:
193  reg[rd] = reg[rs] < reg[rt];
194  break;
195  case SLTU:
196  reg[rd] = (unsigned int) reg[rs] < (unsigned int) reg[rt];
197  break;
198 
199  case JR:
200  pc = reg[rs];
201  break;
202  default:
203  pc = 0; // error
204  break;
205  }
206  break;
207 
208  case J:
209  tgtadr = ins & 0x3ffffff;
210  pc = tgtadr << 2;
211  break;
212  case JAL:
213  tgtadr = ins & 0x3ffffff;
214  reg[31] = pc;
215  pc = tgtadr << 2;
216  break;
217 
218  default:
219 
220  address = ins & 0xffff;
221  rt = (ins >> 16) & 0x1f;
222  rs = (ins >> 21) & 0x1f;
223  switch (op)
224  {
225  case ADDIU:
226  reg[rt] = reg[rs] + address;
227  break;
228 
229  case ANDI:
230  reg[rt] = reg[rs] & (unsigned short) address;
231  break;
232  case ORI:
233  reg[rt] = reg[rs] | (unsigned short) address;
234  break;
235  case XORI:
236  reg[rt] = reg[rs] ^ (unsigned short) address;
237  break;
238 
239  case LW:
240  reg[rt] = dmem[DADDR (reg[rs] + address)];
241  break;
242  case SW:
243  dmem[DADDR (reg[rs] + address)] = reg[rt];
244  break;
245 
246  case LUI:
247  reg[rt] = address << 16;
248  break;
249 
250  case BEQ:
251  if (reg[rs] == reg[rt])
252  pc = pc - 4 + (address << 2);
253  break;
254  case BNE:
255  if (reg[rs] != reg[rt])
256  pc = pc - 4 + (address << 2);
257  break;
258  case BGEZ:
259  if (reg[rs] >= 0)
260  pc = pc - 4 + (address << 2);
261  break;
262 
263  case SLTI:
264  reg[rt] = reg[rs] < address;
265  break;
266 
267  case SLTIU:
268  reg[rt] = (unsigned int) reg[rs] < (unsigned short) address;
269  break;
270 
271  default:
272  pc = 0; /* error */
273  break;
274  }
275  break;
276  }
277  reg[0] = 0;
278  *n_inst = *n_inst + 1;
279  }
280  while (pc != 0);
282 }
283 
284 #ifdef DWARV
285 int
286 main ()
287 {
288  long long hilo;
289  int reg[32];
290  int Hi;
291  int Lo;
292  int pc = 0;
293  int dmem[64];
294  int j;
295 
296  unsigned int ins;
297  int op;
298  int rs;
299  int rt;
300  int rd;
301  int shamt;
302  int funct;
303  short address;
304  int tgtadr;
305  int *m_A, *m_outData;
306  unsigned long *m_imem;
307  int main_result,i;
308  int n_inst;
309 
310  m_A = (int *)malloc(8 * sizeof(int));
311  m_outData = (int *)malloc(8 * sizeof(int));
312  m_imem = (unsigned long *)malloc(44 * sizeof(unsigned long));
313 
314  for( i = 0; i < 8; i++)
315  {
316  m_A[i] = A[i];
317  m_outData[i] = outData[i];
318  }
319  for( i = 0; i < 44; i++)
320  {
321  m_imem[i] = imem[i];
322  }
323  while (1)
324  {
325 
326  n_inst = 0;
327  main_result = 0;
328 
329  for (i = 0; i < 32; i++)
330  {
331  reg[i] = 0;
332  }
333  reg[29] = 0x7fffeffc;
334 
335  for (i = 0; i < 8; i++)
336  {
337  dmem[i] = m_A[i];
338  }
339 
340  pc = 0x00400000;
341 
342  mips_call(reg, m_imem, &n_inst, dmem);
343 
344  main_result += (n_inst != 611);
345  for (j = 0; j < 8; j++)
346  {
347  main_result += (dmem[j] != m_outData[j]);
348  }
349 
350  printf ("%d\n", main_result);
351  break;
352  }
353  return main_result;
354 }
355 #else
356 int
358 {
359  long long hilo;
360  int reg[32];
361  int Hi;
362  int Lo;
363  int pc = 0;
364  int dmem[64];
365  int j;
366 
367  unsigned int ins;
368  int op;
369  int rs;
370  int rt;
371  int rd;
372  int shamt;
373  int funct;
374  short address;
375  int tgtadr;
376  int n_inst;
377  int i;
378 
379  while (1)
380  {
381 
382  n_inst = 0;
383  main_result = 0;
384 
385  for (i = 0; i < 32; i++)
386  {
387  reg[i] = 0;
388  }
389  reg[29] = 0x7fffeffc;
390 
391  for (i = 0; i < 8; i++)
392  {
393  dmem[i] = A[i];
394  }
395 
396  pc = 0x00400000;
397 
398  mips_call(reg, imem, &n_inst, dmem);
399 
400  main_result += (n_inst != 611);
401  for (j = 0; j < 8; j++)
402  {
403  main_result += (dmem[j] != outData[j]);
404  }
405 
406  printf ("%d\n", main_result);
407  break;
408  }
409  return main_result;
410 }
411 #endif
const int A[8]
Definition: mips.c:91
#define LUI
Definition: mips.c:77
void __builtin_bambu_time_start()
#define BEQ
Definition: mips.c:79
#define JR
Definition: mips.c:65
#define SLT
Definition: mips.c:62
#define AND
Definition: mips.c:54
#define SRLV
Definition: mips.c:60
int main_result
Definition: mips.c:38
void __attribute__((noinline))
Definition: mips.c:103
#define SLLV
Definition: mips.c:59
#define ORI
Definition: mips.c:72
#define SLL
Definition: mips.c:57
#define LW
Definition: mips.c:75
#define MULTU
Definition: mips.c:49
#define IADDR(x)
Definition: mips.c:98
#define J
Definition: mips.c:67
const int outData[8]
Definition: mips.c:92
#define ADDIU
Definition: mips.c:70
#define ADDU
Definition: mips.c:45
#define SLTIU
Definition: mips.c:84
#define SW
Definition: mips.c:76
#define XOR
Definition: mips.c:56
#define SLTI
Definition: mips.c:83
#define BGEZ
Definition: mips.c:81
#define JAL
Definition: mips.c:68
#define MFHI
Definition: mips.c:51
#define OR
Definition: mips.c:55
const unsigned long imem[44]
Definition: imem.h:37
#define ANDI
Definition: mips.c:71
#define SRL
Definition: mips.c:58
int main()
Definition: mips.c:98
#define SUBU
Definition: mips.c:46
#define BNE
Definition: mips.c:80
#define MFLO
Definition: mips.c:52
#define MULT
Definition: mips.c:48
void __builtin_bambu_time_stop()
#define SLTU
Definition: mips.c:63
#define R
Definition: mips.c:43
#define XORI
Definition: mips.c:73
#define DADDR(x)
Definition: mips.c:99

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