PandA-2024.02
mips.c
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1 /*
2 +--------------------------------------------------------------------------+
3 | CHStone : a suite of benchmark programs for C-based High-Level Synthesis |
4 | ======================================================================== |
5 | |
6 | * Collected and Modified : Y. Hara, H. Tomiyama, S. Honda, |
7 | H. Takada and K. Ishii |
8 | Nagoya University, Japan |
9 | |
10 | * Remark : |
11 | 1. This source code is modified to unify the formats of the benchmark |
12 | programs in CHStone. |
13 | 2. Test vectors are added for CHStone. |
14 | 3. If "main_result" is 0 at the end of the program, the program is |
15 | correctly executed. |
16 | 4. Please follow the copyright of each benchmark program. |
17 +--------------------------------------------------------------------------+
18 */
19 /*
20  * Copyright (C) 2008
21  * Y. Hara, H. Tomiyama, S. Honda, H. Takada and K. Ishii
22  * Nagoya University, Japan
23  * All rights reserved.
24  *
25  * Disclaimer of Warranty
26  *
27  * These software programs are available to the user without any license fee or
28  * royalty on an "as is" basis. The authors disclaims any and all warranties,
29  * whether express, implied, or statuary, including any implied warranties or
30  * merchantability or of fitness for a particular purpose. In no event shall the
31  * copyright-holder be liable for any incidental, punitive, or consequential damages
32  * of any kind whatsoever arising from the use of these programs. This disclaimer
33  * of warranty extends to the user of these programs and user's customers, employees,
34  * agents, transferees, successors, and assigns.
35  *
36  */
37 #include <stdio.h>
39 
40 #define R 0
41 
42 #define ADDU 33
43 #define SUBU 35
44 
45 #define MULT 24
46 #define MULTU 25
47 
48 #define MFHI 16
49 #define MFLO 18
50 
51 #define AND 36
52 #define OR 37
53 #define XOR 38
54 #define SLL 0
55 #define SRL 2
56 #define SLLV 4
57 #define SRLV 6
58 
59 #define SLT 42
60 #define SLTU 43
61 
62 #define JR 8
63 
64 #define J 2
65 #define JAL 3
66 
67 #define ADDIU 9
68 #define ANDI 12
69 #define ORI 13
70 #define XORI 14
71 
72 #define LW 35
73 #define SW 43
74 #define LUI 15
75 
76 #define BEQ 4
77 #define BNE 5
78 #define BGEZ 1
79 
80 #define SLTI 10
81 #define SLTIU 11
82 
83 #include "imem.h"
84 /*
85 +--------------------------------------------------------------------------+
86 | * Test Vectors (added for CHStone) |
87 | A : input data |
88 | outData : expected output data |
89 +--------------------------------------------------------------------------+
90 */
91 const int A[8] = { 22, 5, -9, 3, -17, 38, 0, 11 };
92 const int outData[8] = { -17, -9, 0, 3, 5, 11, 22, 38 };
93 
94 #define IADDR(x) (((x)&0x000000ff)>>2)
95 #define DADDR(x) (((x)&0x000000ff)>>2)
96 
97 int
98 main ()
99 {
100  long long hilo;
101  int reg[32];
102  int Hi = 0;
103  int Lo = 0;
104  int pc = 0;
105  int dmem[64]={0};
106  int j;
107 
108  unsigned int ins;
109  int op;
110  int rs;
111  int rt;
112  int rd;
113  int shamt;
114  int funct;
115  short address;
116  int tgtadr;
117 
118  while (1)
119  {
120  int i;
121  int n_inst;
122 
123  n_inst = 0;
124  main_result = 0;
125 
126  for (i = 0; i < 32; i++)
127  {
128  reg[i] = 0;
129  }
130  reg[29] = 0x7fffeffc;
131 
132  for (i = 0; i < 8; i++)
133  {
134  dmem[i] = A[i];
135  }
136 
137  pc = 0x00400000;
138 
139  do
140  {
141  ins = imem[IADDR (pc)];
142  pc = pc + 4;
143 
144  op = ins >> 26;
145 
146  switch (op)
147  {
148  case R:
149  funct = ins & 0x3f;
150  shamt = (ins >> 6) & 0x1f;
151  rd = (ins >> 11) & 0x1f;
152  rt = (ins >> 16) & 0x1f;
153  rs = (ins >> 21) & 0x1f;
154 
155  switch (funct)
156  {
157 
158  case ADDU:
159  reg[rd] = reg[rs] + reg[rt];
160  break;
161  case SUBU:
162  reg[rd] = reg[rs] - reg[rt];
163  break;
164 
165  case MULT:
166  hilo = (long long) reg[rs] * (long long) reg[rt];
167  Lo = hilo & 0x00000000ffffffffULL;
168  Hi = ((int) (hilo >> 32)) & 0xffffffffUL;
169  break;
170  case MULTU:
171  hilo =
172  (unsigned long long) ((unsigned int) (reg[rs])) *
173  (unsigned long long) ((unsigned int) (reg[rt]));
174  Lo = hilo & 0x00000000ffffffffULL;
175  Hi = ((int) (hilo >> 32)) & 0xffffffffUL;
176  break;
177 
178  case MFHI:
179  reg[rd] = Hi;
180  break;
181  case MFLO:
182  reg[rd] = Lo;
183  break;
184 
185  case AND:
186  reg[rd] = reg[rs] & reg[rt];
187  break;
188  case OR:
189  reg[rd] = reg[rs] | reg[rt];
190  break;
191  case XOR:
192  reg[rd] = reg[rs] ^ reg[rt];
193  break;
194  case SLL:
195  reg[rd] = reg[rt] << shamt;
196  break;
197  case SRL:
198  reg[rd] = reg[rt] >> shamt;
199  break;
200  case SLLV:
201  reg[rd] = reg[rt] << reg[rs];
202  break;
203  case SRLV:
204  reg[rd] = reg[rt] >> reg[rs];
205  break;
206 
207  case SLT:
208  reg[rd] = reg[rs] < reg[rt];
209  break;
210  case SLTU:
211  reg[rd] = (unsigned int) reg[rs] < (unsigned int) reg[rt];
212  break;
213 
214  case JR:
215  pc = reg[rs];
216  break;
217  default:
218  pc = 0; // error
219  break;
220  }
221  break;
222 
223  case J:
224  tgtadr = ins & 0x3ffffff;
225  pc = tgtadr << 2;
226  break;
227  case JAL:
228  tgtadr = ins & 0x3ffffff;
229  reg[31] = pc;
230  pc = tgtadr << 2;
231  break;
232 
233  default:
234 
235  address = ins & 0xffff;
236  rt = (ins >> 16) & 0x1f;
237  rs = (ins >> 21) & 0x1f;
238  switch (op)
239  {
240  case ADDIU:
241  reg[rt] = reg[rs] + address;
242  break;
243 
244  case ANDI:
245  reg[rt] = reg[rs] & (unsigned short) address;
246  break;
247  case ORI:
248  reg[rt] = reg[rs] | (unsigned short) address;
249  break;
250  case XORI:
251  reg[rt] = reg[rs] ^ (unsigned short) address;
252  break;
253 
254  case LW:
255  reg[rt] = dmem[DADDR (reg[rs] + address)];
256  break;
257  case SW:
258  dmem[DADDR (reg[rs] + address)] = reg[rt];
259  break;
260 
261  case LUI:
262  reg[rt] = address << 16;
263  break;
264 
265  case BEQ:
266  if (reg[rs] == reg[rt])
267  pc = pc - 4 + (address << 2);
268  break;
269  case BNE:
270  if (reg[rs] != reg[rt])
271  pc = pc - 4 + (address << 2);
272  break;
273  case BGEZ:
274  if (reg[rs] >= 0)
275  pc = pc - 4 + (address << 2);
276  break;
277 
278  case SLTI:
279  reg[rt] = reg[rs] < address;
280  break;
281 
282  case SLTIU:
283  reg[rt] = (unsigned int) reg[rs] < (unsigned short) address;
284  break;
285 
286  default:
287  pc = 0; /* error */
288  break;
289  }
290  break;
291  }
292  reg[0] = 0;
293  n_inst = n_inst + 1;
294  }
295  while (pc != 0);
296 
297  main_result += (n_inst != 611);
298  for (j = 0; j < 8; j++)
299  {
300  main_result += (dmem[j] != outData[j]);
301  }
302 
303  printf ("%d\n", main_result);
304  return main_result;
305  }
306 }
#define JR
Definition: mips.c:62
const int A[8]
Definition: mips.c:91
#define MULT
Definition: mips.c:45
#define LUI
Definition: mips.c:74
int main_result
Definition: mips.c:38
#define LW
Definition: mips.c:72
#define JAL
Definition: mips.c:65
#define SRLV
Definition: mips.c:57
#define SRL
Definition: mips.c:55
#define SUBU
Definition: mips.c:43
#define SLT
Definition: mips.c:59
#define MFHI
Definition: mips.c:48
#define SLTI
Definition: mips.c:80
const int outData[8]
Definition: mips.c:92
#define SLTIU
Definition: mips.c:81
#define MFLO
Definition: mips.c:49
#define SLTU
Definition: mips.c:60
#define SW
Definition: mips.c:73
#define BGEZ
Definition: mips.c:78
#define J
Definition: mips.c:64
#define MULTU
Definition: mips.c:46
#define ADDIU
Definition: mips.c:67
#define SLLV
Definition: mips.c:56
#define ORI
Definition: mips.c:69
#define XORI
Definition: mips.c:70
const unsigned long imem[44]
Definition: imem.h:37
#define ADDU
Definition: mips.c:42
#define SLL
Definition: mips.c:54
#define BNE
Definition: mips.c:77
#define XOR
Definition: mips.c:53
int main()
Definition: mips.c:98
#define R
Definition: mips.c:40
#define BEQ
Definition: mips.c:76
#define IADDR(x)
Definition: mips.c:94
#define ANDI
Definition: mips.c:68
#define AND
Definition: mips.c:51
#define DADDR(x)
Definition: mips.c:95
#define OR
Definition: mips.c:52

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