PandA-2024.02
Write_none_registeredModuleGenerator.cpp
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48 
49 #include "language_writer.hpp"
50 
51 enum in_port
52 {
53  i_clock = 0,
60 };
61 
63 {
64  o_out1 = 0,
66 };
67 
69  : Registrar(_HLSMgr)
70 {
71 }
72 
74  std::ostream& out, structural_objectRef /* mod */, unsigned int /* function_id */, vertex /* op_v */,
75  const HDLWriter_Language language, const std::vector<ModuleGenerator::parameter>& /* _p */,
76  const std::vector<ModuleGenerator::parameter>& _ports_in, const std::vector<ModuleGenerator::parameter>& _ports_out,
77  const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
78 {
79  THROW_ASSERT(_ports_in.size() >= i_last, "");
80  THROW_ASSERT(_ports_out.size() >= o_last, "");
81  if(language == HDLWriter_Language::VHDL)
82  {
83  out << "constant ones : std_logic_vector(\\" << _ports_out[o_out1].name << "\\'range) := (others => '1');\n";
84  out << "constant threezeros : std_logic_vector(2 downto 0) := (others => '0');\n";
85  out << "begin\n";
86  out << "process(clock,reset)\n";
87  out << " variable \\" << _ports_out[o_out1].name << "_0\\ : std_logic_vector("
88  << (_ports_out[o_out1].type_size - 1) << " downto 0);\n";
89  out << "begin\n";
90  out << " if (1RESET_VALUE) then\n";
91  out << " \\" << _ports_out[o_out1].name << "\\ <= (others => '0');\n";
92  out << " elsif (clock'event and clock='1') then\n";
93  out << " if(unsigned(" << _ports_in[i_start].name << ") /= 0 ) then\n";
94  out << " \\" << _ports_out[o_out1].name << "\\ <= std_logic_vector(resize(unsigned(" << _ports_in[i_in2].name
95  << "), " << _ports_out[o_out1].type_size << "));\n";
96  out << " end if;\n";
97  out << " end if;\n";
98  out << "end process;\n";
99  }
100  else
101  {
102  out << "reg [" << (_ports_out[o_out1].type_size - 1) << ":0] " << _ports_out[o_out1].name << ";\n";
103 
104  out << "always @(posedge clock 1RESET_EDGE)\n";
105  out << "begin\n";
106  out << " if (1RESET_VALUE)\n";
107  out << " " << _ports_out[o_out1].name << " <= 0;\n";
108  out << " else if(" << _ports_in[i_start].name << ")\n";
109  out << " " << _ports_out[o_out1].name << " <= " << _ports_in[i_in2].name << ";\n";
110  out << "end\n";
111  }
112 }
HDLWriter_Language
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
boost::graph_traits< graph >::vertex_descriptor vertex
vertex definition.
Definition: graph.hpp:1303
void InternalExec(std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final
Write_none_registeredModuleGenerator(const HLS_managerRef &HLSMgr)
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
#define THROW_ASSERT(cond, str_expr)
helper function used to check an assert and if needed to throw an error in a standard way ...
Definition: exceptions.hpp:289

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