PandA-2024.02
OpenP1NModuleGenerator.cpp
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47 #include "OpenP1NModuleGenerator.hpp"
48 
49 #include "hls_manager.hpp"
50 #include "language_writer.hpp"
51 #include "memory.hpp"
52 #include <fcntl.h>
53 
54 OpenP1NModuleGenerator::OpenP1NModuleGenerator(const HLS_managerRef& _HLSMgr) : Registrar(_HLSMgr)
55 {
56 }
57 
58 void OpenP1NModuleGenerator::InternalExec(std::ostream& out, structural_objectRef /* mod */,
59  unsigned int /* function_id */, vertex /* op_v */,
60  const HDLWriter_Language /* language */,
61  const std::vector<ModuleGenerator::parameter>& _p,
62  const std::vector<ModuleGenerator::parameter>& /* _ports_in */,
63  const std::vector<ModuleGenerator::parameter>& /* _ports_out */,
64  const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
65 {
66  const auto data_bus_bitsize = STR(HLSMgr->Rmem->get_bus_data_bitsize());
67  const auto addr_bus_bitsize = STR(HLSMgr->get_address_bitsize());
68  const auto size_bus_bitsize = STR(HLSMgr->Rmem->get_bus_size_bitsize());
69 
70  out << " // verilator lint_off LITENDIAN\n";
71  out << "parameter MAX_BUFF_SIZE = 256;\n";
72  out << "reg [0:8*MAX_BUFF_SIZE-1] buffer_name;\n";
73  out << "\n";
74  out << " `ifndef _SIM_HAVE_CLOG2\n";
75  out << " function integer log2;\n";
76  out << " input integer value;\n";
77  out << " integer temp_value;\n";
78  out << " begin\n";
79  out << " temp_value = value-1;\n";
80  out << " for (log2=0; temp_value>0; log2=log2+1)\n";
81  out << " temp_value = temp_value>>1;\n";
82  out << " end\n";
83  out << " endfunction\n";
84  out << " `endif\n";
85  out << "\n";
86  out << " `ifdef _SIM_HAVE_CLOG2\n";
87  out << " parameter nbits_buffer = $clog2(MAX_BUFF_SIZE);\n";
88  out << " `else\n";
89  out << " parameter nbits_buffer = log2(MAX_BUFF_SIZE);\n";
90  out << " `endif\n";
91 
92  std::string sensitivity;
93  for(auto i = 0U; i < _p.size(); i++)
94  {
95  sensitivity += " or " + _p[i].name;
96  }
97 
98  std::string modes = "in2";
99 
100  std::string flags_string = "(" + modes + " & " + STR(O_RDWR) + ") != 0 && (" + modes + " & " + STR(O_APPEND) +
101  ") ? \"a+b\" : ((" + modes + " & " + STR(O_RDWR) + ") != 0 ? \"r+b\" : ((" + modes +
102  " & " + STR(O_WRONLY) + ") != 0 && (" + modes + " & " + STR(O_APPEND) + ") ? \"ab\" : (" +
103  modes + " & " + STR(O_WRONLY) + ") != 0 ? \"wb\" : \"rb\"" + "))";
104 
105  const auto fsm =
106  " reg [nbits_buffer-1:0] _present_index;\n"
107  " reg [nbits_buffer-1:0] _next_index;\n"
108  " reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer;\n"
109  " reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer;\n"
110  " reg done_port;\n"
111  " wire mem_done_port;\n"
112  " reg signed [BITSIZE_out1-1:0] temp_out1;\n"
113  " \n"
114  " parameter [1:0] S_0 = 2'd0,\n"
115  " S_1 = 2'd1,\n"
116  " S_2 = 2'd2,\n"
117  " S_3 = 2'd3;\n"
118  " reg [3:0] _present_state;\n"
119  " reg [3:0] _next_state;\n"
120  " reg [63:0] data1;\n"
121  " reg [7:0] data1_size;\n"
122  " wire [" +
123  data_bus_bitsize +
124  "-1:0] mem_out1;\n"
125  " reg [" +
126  addr_bus_bitsize +
127  "-1:0] mem_in2;\n"
128  " reg [" +
129  size_bus_bitsize +
130  "-1:0] mem_in3;\n"
131  " reg mem_start_port;\n"
132  " reg mem_sel_LOAD;\n"
133  " MEMORY_CTRL_P1N #(.BITSIZE_in1(" +
134  data_bus_bitsize + "), .BITSIZE_in2(" + addr_bus_bitsize + "), .BITSIZE_in3(" + size_bus_bitsize +
135  "), .BITSIZE_in4(1), .BITSIZE_out1(" + data_bus_bitsize +
136  "), .BITSIZE_Min_oe_ram(BITSIZE_Min_oe_ram), .PORTSIZE_Min_oe_ram(PORTSIZE_Min_oe_ram), "
137  ".BITSIZE_Min_we_ram(BITSIZE_Min_we_ram), .PORTSIZE_Min_we_ram(PORTSIZE_Min_we_ram), "
138  ".BITSIZE_Mout_oe_ram(BITSIZE_Mout_oe_ram), .PORTSIZE_Mout_oe_ram(PORTSIZE_Mout_oe_ram), "
139  ".BITSIZE_Mout_we_ram(BITSIZE_Mout_we_ram), .PORTSIZE_Mout_we_ram(PORTSIZE_Mout_we_ram), "
140  ".BITSIZE_M_DataRdy(BITSIZE_M_DataRdy), .PORTSIZE_M_DataRdy(PORTSIZE_M_DataRdy), "
141  ".BITSIZE_Min_addr_ram(BITSIZE_Min_addr_ram), .PORTSIZE_Min_addr_ram(PORTSIZE_Min_addr_ram), "
142  ".BITSIZE_Mout_addr_ram(BITSIZE_Mout_addr_ram), .PORTSIZE_Mout_addr_ram(PORTSIZE_Mout_addr_ram), "
143  ".BITSIZE_M_Rdata_ram(BITSIZE_M_Rdata_ram), .PORTSIZE_M_Rdata_ram(PORTSIZE_M_Rdata_ram), "
144  ".BITSIZE_Min_Wdata_ram(BITSIZE_Min_Wdata_ram), .PORTSIZE_Min_Wdata_ram(PORTSIZE_Min_Wdata_ram), "
145  ".BITSIZE_Mout_Wdata_ram(BITSIZE_Mout_Wdata_ram), .PORTSIZE_Mout_Wdata_ram(PORTSIZE_Mout_Wdata_ram), "
146  ".BITSIZE_Min_data_ram_size(BITSIZE_Min_data_ram_size), "
147  ".PORTSIZE_Min_data_ram_size(PORTSIZE_Min_data_ram_size), "
148  ".BITSIZE_Mout_data_ram_size(BITSIZE_Mout_data_ram_size), "
149  ".PORTSIZE_Mout_data_ram_size(PORTSIZE_Mout_data_ram_size), .BITSIZE_access_allowed(BITSIZE_access_allowed), "
150  ".PORTSIZE_access_allowed(PORTSIZE_access_allowed), .BITSIZE_access_request(BITSIZE_access_request), "
151  ".PORTSIZE_access_request(PORTSIZE_access_request)) MEMORY_CTRL_P1N_instance (.done_port(mem_done_port), "
152  ".out1(mem_out1), .Mout_oe_ram(Mout_oe_ram), .Mout_we_ram(Mout_we_ram), .Mout_addr_ram(Mout_addr_ram), "
153  ".Mout_Wdata_ram(Mout_Wdata_ram), .Mout_data_ram_size(Mout_data_ram_size), .access_request(access_request), "
154  ".clock(clock), .start_port(mem_start_port), .in1(0), .in2(mem_in2), .in3(mem_in3), .in4(1), "
155  ".sel_LOAD(mem_sel_LOAD), .sel_STORE(1'b0), .Min_oe_ram(Min_oe_ram), .Min_we_ram(Min_we_ram), "
156  ".Min_addr_ram(Min_addr_ram), .M_Rdata_ram(M_Rdata_ram), .Min_Wdata_ram(Min_Wdata_ram), "
157  ".Min_data_ram_size(Min_data_ram_size), .M_DataRdy(M_DataRdy), .access_allowed(access_allowed));\n"
158  "\n"
159  " \n"
160  " always @(posedge clock 1RESET_EDGE)\n"
161  " if (1RESET_VALUE)\n"
162  " begin\n"
163  " _present_state <= S_0;\n"
164  " _present_pointer <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
165  " _present_index <= {nbits_buffer{1'b0}};\n"
166  " end\n"
167  " else\n"
168  " begin\n"
169  " _present_state <= _next_state;\n"
170  " _present_pointer <= _next_pointer;\n"
171  " _present_index <= _next_index;\n"
172  " end\n"
173  " \n"
174  " assign out1 = {1'b0,temp_out1[30:0]};"
175  " always @(_present_state or _present_pointer or _present_index or start_port or mem_done_port or Min_we_ram "
176  "or Min_oe_ram or Min_Wdata_ram or Min_addr_ram or Min_data_ram_size" +
177  sensitivity +
178  " or mem_out1)\n"
179  " begin\n"
180  " done_port = 1'b0;\n"
181  " _next_state = _present_state;\n"
182  " _next_pointer = _present_pointer;\n"
183  " _next_index = _present_index;\n"
184  " mem_sel_LOAD = 1'b0;\n"
185  " mem_in2=" +
186  addr_bus_bitsize +
187  "'d0;\n"
188  " mem_in3=" +
189  size_bus_bitsize +
190  "'d0;\n"
191  " mem_start_port = 1'b0;\n"
192  " case (_present_state)\n"
193  " S_0:\n"
194  " if(start_port)\n"
195  " begin\n"
196  " _next_pointer=0;\n"
197  " _next_index={nbits_buffer{1'b0}};\n"
198  " _next_state=S_1; \n"
199  " buffer_name=0; \n"
200  " end\n"
201  " \n"
202  " S_1:\n"
203  " begin\n"
204  " mem_in2 = in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer;\n"
205  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
206  " mem_sel_LOAD=1'b1;\n"
207  " mem_start_port=1'b1;\n"
208  " if(mem_done_port)\n"
209  " begin\n"
210  " buffer_name[_present_index*8 +:8] = mem_out1[7:0];\n"
211  " if(mem_out1[7:0] == 8'd0)\n"
212  " _next_state=S_2;\n"
213  " else\n"
214  " _next_state=S_3;\n"
215  " end\n"
216  " end\n"
217  " S_2:\n"
218  " begin\n"
219  "// synthesis translate_off\n"
220  " temp_out1 = $fopen(buffer_name, " +
221  flags_string +
222  ");\n"
223  "// synthesis translate_on\n"
224  " done_port = 1'b1;\n"
225  " _next_state=S_0;\n"
226  " end\n"
227  " S_3:\n"
228  " begin\n"
229  " if(!mem_done_port)\n"
230  " begin\n"
231  " _next_pointer=_present_pointer+1'd1;\n"
232  " _next_index=_present_index+1'd1;\n"
233  " _next_state=S_1;\n"
234  " end\n"
235  " end\n"
236  " endcase\n"
237  " end\n";
238 
239  out << fsm;
240  out << " // verilator lint_on LITENDIAN\n";
241 }
hls_manager.hpp
Data structure representing the entire HLS information.
STR
#define STR(s)
Macro which performs a lexical_cast to a string.
Definition: string_manipulation.hpp:52
HDLWriter_Language
HDLWriter_Language
Definition: language_writer.hpp:78
language_writer.hpp
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
vertex
boost::graph_traits< graph >::vertex_descriptor vertex
vertex definition.
Definition: graph.hpp:1303
OpenP1NModuleGenerator::InternalExec
void InternalExec(std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final
Definition: OpenP1NModuleGenerator.cpp:58
bit_lattice::U
OpenP1NModuleGenerator::OpenP1NModuleGenerator
OpenP1NModuleGenerator(const HLS_managerRef &HLSMgr)
Definition: OpenP1NModuleGenerator.cpp:54
refcount
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
memory.hpp
Datastructure to represent memory information in high-level synthesis.
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