PandA-2024.02
OpenNModuleGenerator.cpp
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47 #include "OpenNModuleGenerator.hpp"
48 
49 #include "language_writer.hpp"
50 #include <fcntl.h>
51 
52 OpenNModuleGenerator::OpenNModuleGenerator(const HLS_managerRef& _HLSMgr) : Registrar(_HLSMgr)
53 {
54 }
55 
56 void OpenNModuleGenerator::InternalExec(std::ostream& out, structural_objectRef /* mod */,
57  unsigned int /* function_id */, vertex /* op_v */,
58  const HDLWriter_Language /* language */,
59  const std::vector<ModuleGenerator::parameter>& /* _p */,
60  const std::vector<ModuleGenerator::parameter>& /* _ports_in */,
61  const std::vector<ModuleGenerator::parameter>& /* _ports_out */,
62  const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
63 {
64  out << " // verilator lint_off LITENDIAN\n";
65  out << "parameter MAX_BUFF_SIZE = 256;\n";
66  out << "reg [0:8*MAX_BUFF_SIZE-1] buffer_name;\n";
67  out << "reg [0:8*MAX_BUFF_SIZE-1] buffer_name_old;\n";
68  out << "\n";
69  out << " `ifndef _SIM_HAVE_CLOG2\n";
70  out << " function integer log2;\n";
71  out << " input integer value;\n";
72  out << " integer temp_value;\n";
73  out << " begin\n";
74  out << " temp_value = value-1;\n";
75  out << " for (log2=0; temp_value>0; log2=log2+1)\n";
76  out << " temp_value = temp_value>>1;\n";
77  out << " end\n";
78  out << " endfunction\n";
79  out << " `endif\n";
80  out << "\n";
81  out << " `ifdef _SIM_HAVE_CLOG2\n";
82  out << " parameter nbits_buffer = $clog2(MAX_BUFF_SIZE);\n";
83  out << " `else\n";
84  out << " parameter nbits_buffer = log2(MAX_BUFF_SIZE);\n";
85  out << " `endif\n";
86 
87  std::string modes = "in2";
88 
89  std::string flags_string = "(" + modes + " & " + STR(O_RDWR) + ") != 0 && (" + modes + " & " + STR(O_APPEND) +
90  ") ? \"a+b\" : ((" + modes + " & " + STR(O_RDWR) + ") != 0 ? \"r+b\" : ((" + modes +
91  " & " + STR(O_WRONLY) + ") != 0 && (" + modes + " & " + STR(O_APPEND) + ") ? \"ab\" : (" +
92  modes + " & " + STR(O_WRONLY) + ") != 0 ? \"wb\" : \"rb\"" + "))";
93 
94  const auto fsm =
95  "reg [nbits_buffer-1:0] _present_index;\n"
96  " reg [nbits_buffer-1:0] _next_index;\n"
97  " reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer;\n"
98  " reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer;\n"
99  " reg done_port;\n"
100  " reg signed [BITSIZE_out1-1:0] temp_out1;\n"
101  " reg [PORTSIZE_Mout_oe_ram-1:0] Mout_oe_ram;\n"
102  " reg [PORTSIZE_Mout_we_ram-1:0] Mout_we_ram;\n"
103  " reg [(PORTSIZE_Mout_addr_ram*BITSIZE_Mout_addr_ram)+(-1):0] Mout_addr_ram;\n"
104  " reg [(PORTSIZE_Mout_Wdata_ram*BITSIZE_Mout_Wdata_ram)+(-1):0] Mout_Wdata_ram;\n"
105  " reg [(PORTSIZE_Mout_data_ram_size*BITSIZE_Mout_data_ram_size)+(-1):0] Mout_data_ram_size;\n"
106  " reg active_request;\n"
107  " reg active_request_next;\n"
108  " reg active_request_now;\n"
109  " reg M_DataRdy_reg;\n"
110  " reg [BITSIZE_M_Rdata_ram-1:0]M_Rdata_ram_reg;\n"
111  " \n"
112  " parameter [1:0] S_0 = 2'd0,\n"
113  " S_1 = 2'd1,\n"
114  " S_2 = 2'd2;\n"
115  " reg [1:0] _present_state 1INIT_ZERO_VALUE;\n"
116  " reg [1:0] _next_state;\n"
117  " reg [63:0] data1;\n"
118  " reg [7:0] data1_size;\n"
119  " \n"
120  " always @(posedge clock 1RESET_EDGE)\n"
121  " if (1RESET_VALUE)\n"
122  " begin\n"
123  " _present_state <= S_0;\n"
124  " _present_pointer <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
125  " _present_index <= {nbits_buffer{1'b0}};\n"
126  " buffer_name_old <= {8*MAX_BUFF_SIZE{1'b0}};\n"
127  " M_DataRdy_reg <= 0;\n"
128  " M_Rdata_ram_reg <= 0;\n"
129  " end\n"
130  " else\n"
131  " begin\n"
132  " _present_state <= _next_state;\n"
133  " _present_pointer <= _next_pointer;\n"
134  " _present_index <= _next_index;\n"
135  " buffer_name_old <= buffer_name;\n"
136  " M_DataRdy_reg <= M_DataRdy;\n"
137  " M_Rdata_ram_reg <= M_Rdata_ram;\n"
138  " end\n"
139  " \n"
140  " assign out1 = {1'b0,temp_out1[30:0]};\n"
141  " always @(posedge clock 1RESET_EDGE)\n"
142  " begin\n"
143  " if (1RESET_VALUE)\n"
144  " begin\n"
145  " active_request <= 0;\n"
146  " end\n"
147  " else\n"
148  " begin\n"
149  " active_request <= active_request_next;\n"
150  " end\n"
151  " end\n"
152  " always @(*)\n"
153  " begin\n"
154  " Mout_we_ram = Min_we_ram;\n"
155  " Mout_Wdata_ram = Min_Wdata_ram;\n"
156  " Mout_oe_ram = Min_oe_ram;\n"
157  " Mout_addr_ram = Min_addr_ram;\n"
158  " Mout_data_ram_size = Min_data_ram_size;\n"
159  " Mout_oe_ram = Min_oe_ram;\n"
160  " Mout_addr_ram = Min_addr_ram;\n"
161  " Mout_data_ram_size = Min_data_ram_size;\n"
162  " done_port = 1'b0;\n"
163  " _next_state = _present_state;\n"
164  " _next_pointer = _present_pointer;\n"
165  " _next_index = _present_index;\n"
166  " active_request_next = 1'b0;\n"
167  " active_request_now = 1'b0;\n"
168  " buffer_name = buffer_name_old;\n"
169  " case (_present_state)\n"
170  " S_0:\n"
171  " if(start_port)\n"
172  " begin\n"
173  " _next_pointer=0;\n"
174  " _next_index={nbits_buffer{1'b0}};\n"
175  " _next_state=S_1; \n"
176  " active_request_next = 1'b1;\n"
177  " active_request_next = 1'b1;\n"
178  " buffer_name=0; \n"
179  " end\n"
180  " S_1:\n"
181  " begin\n"
182  " if(M_DataRdy_reg)\n"
183  " begin\n"
184  " buffer_name[_present_index*8 +:8] = M_Rdata_ram_reg[7:0];\n"
185  " if(M_Rdata_ram_reg[7:0] == 8'd0)\n"
186  " _next_state=S_2;\n"
187  " else\n"
188  " begin\n"
189  " _next_state=S_1;\n"
190  " _next_pointer = _present_pointer + 1'd1;\n"
191  " _next_index = _present_index + 1'd1;\n"
192  " active_request_now = 1'b1;\n"
193  " end\n"
194  " end\n"
195  " Mout_addr_ram[BITSIZE_Mout_addr_ram-1:0] = (in1[BITSIZE_Mout_addr_ram-1:0]+_next_pointer) & "
196  "{BITSIZE_Mout_addr_ram{active_request || active_request_now}};\n"
197  " Mout_data_ram_size[BITSIZE_Mout_data_ram_size-1:0] = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8} "
198  "& "
199  "{BITSIZE_Mout_data_ram_size{active_request || active_request_now}};\n"
200  " Mout_oe_ram[0] = active_request || active_request_now;\n"
201  " end\n"
202  " S_2:\n"
203  " begin\n"
204  "// synthesis translate_off\n"
205  " temp_out1 = $fopen(buffer_name, " +
206  flags_string +
207  ");\n"
208  "// synthesis translate_on\n"
209  " done_port = 1'b1;\n"
210  " _next_state = S_0;\n"
211  " end\n"
212  " endcase\n"
213  " end\n";
214 
215  out << fsm;
216  out << " // verilator lint_on LITENDIAN\n";
217 }
OpenNModuleGenerator::OpenNModuleGenerator
OpenNModuleGenerator(const HLS_managerRef &HLSMgr)
Definition: OpenNModuleGenerator.cpp:52
STR
#define STR(s)
Macro which performs a lexical_cast to a string.
Definition: string_manipulation.hpp:52
HDLWriter_Language
HDLWriter_Language
Definition: language_writer.hpp:78
language_writer.hpp
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
vertex
boost::graph_traits< graph >::vertex_descriptor vertex
vertex definition.
Definition: graph.hpp:1303
OpenNModuleGenerator::InternalExec
void InternalExec(std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final
Definition: OpenNModuleGenerator.cpp:56
refcount
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
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