70 const DesignFlowManagerConstRef _design_flow_manager)
83 switch(relationship_type)
111 const auto aadl_information =
HLSMgr->aadl_information;
116 auto SM_minimal_interface =
HLS->
top;
120 auto SM_taste_interface =
HLS->
top;
125 SM_taste_interface->set_top_info(module_name, module_type);
133 GetPointer<module>(taste_interface_circuit)->set_description(
"Top circuit for " + module_name);
134 GetPointer<module>(taste_interface_circuit)->set_copyright(
"Copyright (C) 2004-2024 Politecnico di Milano");
135 GetPointer<module>(taste_interface_circuit)->set_authors(
"module automatically generated by bambu");
136 GetPointer<module>(taste_interface_circuit)->set_license(
"PANDA_GPLv3");
139 auto minimal_interface_module = GetPointer<const module>(minimal_interface);
140 minimal_interface->
set_owner(taste_interface_circuit);
141 minimal_interface->
set_id(
"accelerator");
144 GetPointer<module>(taste_interface_circuit)->add_internal_object(minimal_interface);
147 const bool with_memory = [&]() ->
bool {
149 for(
unsigned int i = 0; i < minimal_interface_module->get_in_port_size(); i++)
152 if(GetPointer<port_o>(port_obj)->get_is_memory())
155 if(GetPointer<port_o>(port_obj)->get_id().find(
'M') == 0)
169 SM_taste_interface->add_port(
CLOCK_PORT_NAME, port_o::IN, taste_interface_circuit, clock_type);
172 SM_taste_interface->add_port(
RESET_PORT_NAME, port_o::IN, taste_interface_circuit, reset_type);
175 SM_taste_interface->add_port(
"apbi_psel", port_o::IN, taste_interface_circuit, bool_type);
176 SM_taste_interface->add_port(
"apbi_penable", port_o::IN, taste_interface_circuit, bool_type);
177 SM_taste_interface->add_port(
"apbi_pwrite", port_o::IN, taste_interface_circuit, bool_type);
181 SM_taste_interface->add_port(
"apbi_pwdata", port_o::IN, taste_interface_circuit, word_bool_type);
182 SM_taste_interface->add_port(
"apbi_paddr", port_o::IN, taste_interface_circuit, word_bool_type);
184 SM_taste_interface->add_port(
"apbo_prdata", port_o::OUT, taste_interface_circuit, word_bool_type);
197 const auto number_of_states =
199 ->STG->get_number_of_states();
206 const auto reg_status_update = SM_taste_interface->add_module_from_technology_library(
208 const auto done_port_converter = SM_taste_interface->add_module_from_technology_library(
210 AddSignal(SM_taste_interface, minimal_interface,
DONE_PORT_NAME, done_port_converter,
"in1",
"done_port_output");
211 AddSignal(SM_taste_interface, done_port_converter,
"out1", reg_status_update,
"from_done",
212 "done_port_converter_output");
213 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_pwdata", reg_status_update,
"from_outside");
219 const auto reg_status = SM_taste_interface->add_module_from_technology_library(
221 const auto shift = SM_taste_interface->add_module_from_technology_library(
222 "shift",
"ui_rshift_expr_FU", TM->
get_library(
"ui_rshift_expr_FU"), taste_interface_circuit, TM);
223 shift->SetParameter(
"PRECISION",
"32");
224 GetPointer<port_o>(GetPointer<module>(reg_status)->find_member(
"in1",
port_o_K, reg_status))->type_resize(32);
225 GetPointer<port_o>(GetPointer<module>(reg_status)->find_member(
"out1",
port_o_K, reg_status))->type_resize(32);
226 GetPointer<port_o>(GetPointer<module>(shift)->find_member(
"in1",
port_o_K, shift))->type_resize(32);
227 GetPointer<port_o>(GetPointer<module>(shift)->find_member(
"out1",
port_o_K, shift))->type_resize(32);
228 const auto start_port_converter = SM_taste_interface->add_module_from_technology_library(
231 AddSignal(SM_taste_interface, reg_status,
"out1", shift,
"in1",
"reg_status_output");
232 AddConstant(SM_taste_interface, shift,
"in2",
"3", 3);
233 AddSignal(SM_taste_interface, reg_status,
"out1", reg_status_update,
"current_value",
"reg_status_output");
234 AddSignal(SM_taste_interface, shift,
"out1", start_port_converter,
"in1",
"shift_output");
236 "start_port_converter_output");
237 AddConstant(SM_taste_interface, reg_status,
"wenable",
"1", 1);
238 AddSignal(SM_taste_interface, reg_status_update,
"return_port", reg_status,
"in1",
"reg_status_update_output");
244 unsigned long long int addr_range = aadl_information->exposed_memory_sizes[function_name];
246 for(index = 1; addr_range >= (1ull <<
index); ++
index)
250 const auto relative_address_bitsize =
index;
251 unsigned long long int address_mask = 0;
252 for(index = 0; index < relative_address_bitsize; index++)
254 address_mask += 1ull <<
index;
258 const auto filtered_address = SM_taste_interface->add_module_from_technology_library(
259 "filtered_address",
"ui_bit_and_expr_FU", TM->
get_library(
"ui_bit_and_expr_FU"), taste_interface_circuit, TM);
260 GetPointer<port_o>(GetPointer<module>(filtered_address)->find_member(
"out1",
port_o_K, filtered_address))
262 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_paddr", filtered_address,
"in1");
263 AddConstant(SM_taste_interface, filtered_address,
"in2",
STR(address_mask), 32);
271 ->STG->get_number_of_states() == 1,
275 ->STG->get_number_of_states()));
276 const auto endianess_check = SM_taste_interface->add_module_from_technology_library(
278 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_pwdata", endianess_check,
"arg");
289 ->STG->get_number_of_states() == 1,
291 const auto swap32_in = SM_taste_interface->add_module_from_technology_library(
293 const auto swap32_in_cond_expr = SM_taste_interface->add_module_from_technology_library(
294 "swap32_in_cond_expr",
"ui_cond_expr_FU", TM->
get_library(
"ui_cond_expr_FU"), taste_interface_circuit, TM);
295 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_pwdata", swap32_in,
"x");
300 AddSignal(SM_taste_interface, endianess_check,
"return_port", swap32_in_cond_expr,
"in1",
"endianess_check_output");
301 AddSignal(SM_taste_interface, swap32_in,
"return_port", swap32_in_cond_expr,
"in2",
"swap32_in_output");
302 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_pwdata", swap32_in_cond_expr,
"in3");
307 THROW_ASSERT(aadl_information->function_parameters.find(
"PI_" + function_name) !=
308 aadl_information->function_parameters.end(),
309 "Parameters information of PI_" + function_name +
" not found");
310 for(
const auto& function_parameter : aadl_information->function_parameters.find(
"PI_" + function_name)->second)
312 if(function_parameter.num_registers)
315 THROW_ASSERT(function_parameter.num_registers == 1,
"Multiple registers not supported");
316 const auto param_reg = SM_taste_interface->add_module_from_technology_library(
319 switch(function_parameter.direction)
321 case AadlInformation::AadlParameter::Direction::IN:
324 const auto address_compare = SM_taste_interface->add_module_from_technology_library(
325 "address_compare_" + function_parameter.name,
"ui_eq_expr_FU", TM->
get_library(
"ui_eq_expr_FU"),
326 taste_interface_circuit, TM);
327 const auto port = minimal_interface->
find_member(function_parameter.name,
port_o_K, minimal_interface);
330 GetPointer<port_o>(GetPointer<module>(param_reg)->find_member(
"in1",
port_o_K, param_reg))
331 ->type_resize(port_size);
332 GetPointer<port_o>(GetPointer<module>(param_reg)->find_member(
"out1",
port_o_K, param_reg))
333 ->type_resize(port_size);
336 const auto param_converter = SM_taste_interface->add_module_from_technology_library(
339 GetPointer<port_o>(GetPointer<module>(param_converter)->find_member(
"in1",
port_o_K, param_converter))
341 AddSignal(SM_taste_interface, swap32_in_cond_expr,
"out1", param_converter,
"in1",
342 "endianess_inversion_output");
345 AddSignal(SM_taste_interface, filtered_address,
"out1", address_compare,
"in1",
346 "filtered_address_output");
347 AddConstant(SM_taste_interface, address_compare,
"in2", std::to_string(function_parameter.bambu_address),
349 AddSignal(SM_taste_interface, address_compare,
"out1", param_reg,
"wenable",
"address_compare_output");
350 AddSignal(SM_taste_interface, param_converter,
"out1", param_reg,
"in1",
351 "param_converter_" + function_parameter.name +
"_output");
352 AddSignal(SM_taste_interface, param_reg,
"out1", minimal_interface, function_parameter.name,
353 function_parameter.name +
"_reg_output");
356 case AadlInformation::AadlParameter::Direction::OUT:
362 GetPointer<port_o>(GetPointer<module>(param_reg)->find_member(
"in1",
port_o_K, param_reg))
363 ->type_resize(port_size);
364 GetPointer<port_o>(GetPointer<module>(param_reg)->find_member(
"out1",
port_o_K, param_reg))
365 ->type_resize(port_size);
369 "return_port_output");
376 const auto param_converter = SM_taste_interface->add_module_from_technology_library(
378 taste_interface_circuit, TM);
379 AddSignal(SM_taste_interface, param_reg,
"out1", param_converter,
"in1",
"return_port_reg_output");
382 case AadlInformation::AadlParameter::Direction::INOUT:
392 else if(function_parameter.pointer)
394 AddConstant(SM_taste_interface, minimal_interface, function_parameter.name,
395 STR(function_parameter.bambu_address), 32);
408 memory = SM_taste_interface->add_module_from_technology_library(
"local_memory",
ARRAY_1D_STD_BRAM_NN,
410 memory->
SetParameter(
"address_space_rangesize",
STR(aadl_information->internal_memory_sizes[function_name]));
414 auto bus_data_bitsize =
HLSMgr->Rmem->get_bus_data_bitsize();
415 auto bus_addr_bitsize =
HLSMgr->get_address_bitsize();
416 auto bus_size_bitsize =
HLSMgr->Rmem->get_bus_size_bitsize();
417 auto bus_data_bytesize =
HLSMgr->Rmem->get_bus_data_bitsize() / 8;
419 auto bus_tag_bitsize = 0ull;
420 if(
HLS->
Param->getOption<
bool>(OPT_parse_pragma) &&
HLS->
Param->isOption(OPT_context_switch))
422 bus_tag_bitsize = GetPointer<memory_cs>(
HLSMgr->Rmem)->get_bus_tag_bitsize();
425 const unsigned long long int n_elements =
426 aadl_information->internal_memory_sizes[function_name] / bus_data_bytesize +
427 ((aadl_information->internal_memory_sizes[function_name] % bus_data_bytesize) ? 1 : 0);
431 std::string init_filename_a =
GetPath(function_name +
"_a.data");
432 std::string init_filename_b =
GetPath(function_name +
"_b.data");
433 std::ofstream init_file_a(init_filename_a);
434 std::ofstream init_file_b(init_filename_b);
436 memory->
SetParameter(
"MEMORY_INIT_file_a",
"\"\"" + init_filename_a +
"\"\"");
437 memory->
SetParameter(
"MEMORY_INIT_file_b",
"\"\"" + init_filename_b +
"\"\"");
439 for(
unsigned int row_index = 0; row_index < n_elements; row_index++)
441 init_file_a << std::string(bus_data_bitsize / 2,
'0') << std::endl;
442 init_file_b << std::string(bus_data_bitsize / 2,
'0') << std::endl;
447 for(
unsigned int i = 0; i < GetPointer<module>(memory)->get_in_port_size(); i++)
452 GetPointer<port_o>(port)->add_n_ports(2, port);
458 in1_port->type_resize(
HLSMgr->Rmem->get_bus_data_bitsize());
460 in2_port->type_resize(
HLSMgr->get_address_bitsize());
462 in3_port->type_resize(
HLSMgr->Rmem->get_bus_size_bitsize());
466 AddConstant(SM_taste_interface, memory,
"in4[0]",
"1", 1);
467 AddConstant(SM_taste_interface, memory,
"in4[1]",
"1", 1);
469 for(
unsigned int i = 0; i < GetPointer<module>(memory)->get_out_port_size(); i++)
474 GetPointer<port_o>(port)->add_n_ports(2, port);
480 mem_signals.insert(std::pair<std::string, std::string>(
"M_DataRdy",
"Sout_DataRdy"));
481 mem_signals.insert(std::pair<std::string, std::string>(
"M_Rdata_ram",
"Sin_Rdata_ram"));
482 mem_signals.insert(std::pair<std::string, std::string>(
"Mout_addr_ram",
"S_addr_ram"));
483 mem_signals.insert(std::pair<std::string, std::string>(
"Mout_data_ram_size",
"S_data_ram_size"));
484 mem_signals.insert(std::pair<std::string, std::string>(
"Mout_oe_ram",
"S_oe_ram"));
485 mem_signals.insert(std::pair<std::string, std::string>(
"Mout_we_ram",
"S_we_ram"));
486 mem_signals.insert(std::pair<std::string, std::string>(
"Mout_Wdata_ram",
"S_Wdata_ram"));
488 for(
const auto& mem_signal : mem_signals)
495 "---Connecting " + port1->get_path() +
" to " + port2->get_path());
498 AddConstant(SM_taste_interface, memory,
"Sin_DataRdy[0]",
STR(0), 1);
499 AddConstant(SM_taste_interface, memory,
"Sin_DataRdy[1]",
STR(0), 1);
500 AddConstant(SM_taste_interface, memory,
"proxy_sel_LOAD[0]",
STR(0), 1);
501 AddConstant(SM_taste_interface, memory,
"proxy_sel_LOAD[1]",
STR(0), 1);
502 AddConstant(SM_taste_interface, memory,
"proxy_sel_STORE[0]",
STR(0), 1);
503 AddConstant(SM_taste_interface, memory,
"proxy_sel_STORE[1]",
STR(0), 1);
505 proxy_in1_port->type_resize(
HLSMgr->Rmem->get_bus_data_bitsize());
507 proxy_in2_port->type_resize(
HLSMgr->get_address_bitsize());
509 proxy_in3_port->type_resize(
HLSMgr->Rmem->get_bus_size_bitsize());
510 AddConstant(SM_taste_interface, memory,
"proxy_in1[0]",
STR(0),
HLSMgr->Rmem->get_bus_data_bitsize());
511 AddConstant(SM_taste_interface, memory,
"proxy_in1[1]",
STR(0),
HLSMgr->Rmem->get_bus_data_bitsize());
514 AddConstant(SM_taste_interface, memory,
"proxy_in3[0]",
STR(0),
HLSMgr->Rmem->get_bus_size_bitsize());
515 AddConstant(SM_taste_interface, memory,
"proxy_in3[1]",
STR(0),
HLSMgr->Rmem->get_bus_size_bitsize());
523 ->STG->get_number_of_states() == 1,
525 const auto memory_translation = SM_taste_interface->add_module_from_technology_library(
527 taste_interface_circuit, TM);
528 AddSignal(SM_taste_interface, filtered_address,
"out1", memory_translation,
"arg",
"memory_translation_arg");
539 ->STG->get_number_of_states() == 1,
541 const auto data_size = SM_taste_interface->add_module_from_technology_library(
543 AddSignal(SM_taste_interface, filtered_address,
"out1", data_size,
"arg",
"data_size_arg");
554 ->STG->get_number_of_states() == 1,
556 const auto memory_enabling = SM_taste_interface->add_module_from_technology_library(
558 AddSignal(SM_taste_interface, filtered_address,
"out1", memory_enabling,
"arg",
"memory_enabling_arg");
564 const auto memory_enabling_converter = SM_taste_interface->add_module_from_technology_library(
566 taste_interface_circuit, TM);
567 const auto actual_memory_enabling = SM_taste_interface->add_module_from_technology_library(
568 "actual_memory_enabling",
"ui_bit_and_expr_FU", TM->
get_library(
"ui_bit_and_expr_FU"),
569 taste_interface_circuit, TM);
570 AddSignal(SM_taste_interface, memory_enabling,
"return_port", memory_enabling_converter,
"in1",
571 "memory_enabling_output");
572 AddSignal(SM_taste_interface, memory_enabling_converter,
"out1", actual_memory_enabling,
"in1",
573 "memory_enabling_converter_output");
574 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_psel", actual_memory_enabling,
"in2");
577 const auto not_write = SM_taste_interface->add_module_from_technology_library(
578 "load",
"ui_bit_not_expr_FU", TM->
get_library(
"ui_bit_not_expr_FU"), taste_interface_circuit, TM);
579 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_pwrite", not_write,
"in1");
582 const auto sel_LOAD = SM_taste_interface->add_module_from_technology_library(
583 "sel_LOAD",
"ui_bit_and_expr_FU", TM->
get_library(
"ui_bit_and_expr_FU"), taste_interface_circuit, TM);
584 AddSignal(SM_taste_interface, actual_memory_enabling,
"out1", sel_LOAD,
"in1",
"actual_memory_enabling_output");
585 AddSignal(SM_taste_interface, not_write,
"out1", sel_LOAD,
"in2",
"not_write_output");
588 const auto sel_STORE = SM_taste_interface->add_module_from_technology_library(
589 "sel_STORE",
"ui_bit_and_expr_FU", TM->
get_library(
"ui_bit_and_expr_FU"), taste_interface_circuit, TM);
590 AddSignal(SM_taste_interface, actual_memory_enabling,
"out1", sel_STORE,
"in1",
"actual_memory_enabling_output");
591 AddConnection(SM_taste_interface, taste_interface_circuit,
"apbi_pwrite", sel_STORE,
"in2");
594 AddSignal(SM_taste_interface, swap32_in_cond_expr,
"out1", memory,
"in1[0]",
"endianess_inversion_output");
595 AddConstant(SM_taste_interface, memory,
"in1[1]",
"0",
HLSMgr->Rmem->get_bus_data_bitsize());
597 const auto in2_converter = SM_taste_interface->add_module_from_technology_library(
600 AddSignal(SM_taste_interface, in2_converter,
"out1", memory,
"in2[0]",
"in2_0");
601 AddConstant(SM_taste_interface, memory,
"in2[1]",
"0",
HLSMgr->get_address_bitsize());
603 const auto in3_converter = SM_taste_interface->add_module_from_technology_library(
606 AddSignal(SM_taste_interface, in3_converter,
"out1", memory,
"in3[0]",
"in3_0");
607 AddConstant(SM_taste_interface, memory,
"in3[1]",
"0",
HLSMgr->Rmem->get_bus_size_bitsize());
609 AddSignal(SM_taste_interface, sel_LOAD,
"out1", memory,
"sel_LOAD[0]",
"sel_LOAD_output");
610 AddConstant(SM_taste_interface, memory,
"sel_LOAD[1]",
"0", 1);
612 AddSignal(SM_taste_interface, sel_STORE,
"out1", memory,
"sel_STORE[0]",
"sel_STORE_output");
613 AddConstant(SM_taste_interface, memory,
"sel_STORE[1]",
"0", 1);
624 ->STG->get_number_of_states() == 1,
626 const auto output_multiplexer = SM_taste_interface->add_module_from_technology_library(
629 AddSignal(SM_taste_interface, filtered_address,
"out1", output_multiplexer,
"address",
"memory_enabling_arg");
630 AddSignal(SM_taste_interface, reg_status,
"out1", output_multiplexer,
"reg_status",
"reg_status_output");
635 "return_port_output");
639 AddSignal(SM_taste_interface, memory,
"out1[0]", output_multiplexer,
"from_memory",
"from_memory_output");
640 const auto fake_register = SM_taste_interface->add_module_from_technology_library(
642 GetPointer<port_o>(GetPointer<module>(fake_register)->find_member(
"in1",
port_o_K, fake_register))
644 GetPointer<port_o>(GetPointer<module>(fake_register)->find_member(
"out1",
port_o_K, fake_register))
646 AddSignal(SM_taste_interface, memory,
"out1[1]", fake_register,
"in1",
"fake_signal");
655 ->STG->get_number_of_states() == 1,
657 const auto swap32_out = SM_taste_interface->add_module_from_technology_library(
659 const auto swap32_out_cond_expr = SM_taste_interface->add_module_from_technology_library(
660 "swap32_iout_cond_expr",
"ui_cond_expr_FU", TM->
get_library(
"ui_cond_expr_FU"), taste_interface_circuit, TM);
668 AddSignal(SM_taste_interface, endianess_check,
"return_port", swap32_out_cond_expr,
"in1",
"endianess_check_output");
669 AddSignal(SM_taste_interface, swap32_out,
"return_port", swap32_out_cond_expr,
"in2",
"swap32_out_output");
671 "output_multiplexer_output");
672 AddSignal(SM_taste_interface, swap32_out_cond_expr,
"out1", taste_interface_circuit,
"apbo_prdata",
673 "swap32_out_cond_expr_output");
679 function_name +
"_taste_interface paddr pindex");
681 SM_taste_interface->INIT(
true);
683 if(
parameters->getOption<
bool>(OPT_print_dot))
695 const auto function_name =
HLSMgr->CGetFunctionBehavior(
funId)->CGetBehavioralHelper()->get_function_name();
727 const auto TM =
HLSMgr->get_tree_manager();
733 reg_status_function->index);
735 const auto reg_status_step = reg_status_vertex !=
NULL_VERTEX ?
737 ->CGetDesignFlowGraph()
738 ->CGetDesignFlowStepInfo(reg_status_vertex)
740 hls_flow_step_factory->CreateHLSFlowStep(
743 relationship.insert(reg_status_step);
749 endianess_inversion_function->index);
750 const auto endianess_inversion_vertex =
752 const auto endianess_inversion_step =
755 ->CGetDesignFlowGraph()
756 ->CGetDesignFlowStepInfo(endianess_inversion_vertex)
758 hls_flow_step_factory->CreateHLSFlowStep(
761 relationship.insert(endianess_inversion_step);
767 endianess_check_function->index);
769 const auto endianess_check_step = endianess_check_vertex !=
NULL_VERTEX ?
771 ->CGetDesignFlowGraph()
772 ->CGetDesignFlowStepInfo(endianess_check_vertex)
774 hls_flow_step_factory->CreateHLSFlowStep(
777 relationship.insert(endianess_check_step);
783 output_multiplexer_function->index);
784 const auto output_multiplexer_vertex =
786 const auto output_multiplexer_step =
789 ->CGetDesignFlowGraph()
790 ->CGetDesignFlowStepInfo(output_multiplexer_vertex)
792 hls_flow_step_factory->CreateHLSFlowStep(
795 relationship.insert(output_multiplexer_step);
798 if(memory_enabling_function)
802 memory_enabling_function->index);
804 const auto memory_enabling_step =
807 ->CGetDesignFlowGraph()
808 ->CGetDesignFlowStepInfo(memory_enabling_vertex)
810 hls_flow_step_factory->CreateHLSFlowStep(
813 relationship.insert(memory_enabling_step);
819 data_size_function->index);
821 const auto data_size_step = data_size_vertex !=
NULL_VERTEX ?
823 ->CGetDesignFlowGraph()
824 ->CGetDesignFlowStepInfo(data_size_vertex)
826 hls_flow_step_factory->CreateHLSFlowStep(
829 relationship.insert(data_size_step);
835 address_translation_function->index);
836 const auto address_translation_vertex =
838 const auto address_translation_step =
841 ->CGetDesignFlowGraph()
842 ->CGetDesignFlowStepInfo(address_translation_vertex)
844 hls_flow_step_factory->CreateHLSFlowStep(
847 relationship.insert(address_translation_step);
854 const auto function_name =
HLSMgr->CGetFunctionBehavior(
funId)->CGetBehavioralHelper()->get_function_name();
void ComputeRelationships(DesignFlowStepSet &relationship, const DesignFlowStep::RelationshipType relationship_type) override
Compute the relationships of a step with other steps.
bool HasToBeExecuted() const override
Check if this step has actually to be executed.
#define DEBUG_LEVEL_VERY_PEDANTIC
extremely verbose debugging print is performed.
const HLS_managerRef HLSMgr
information about all the HLS synthesis
Data structure representing the entire HLS information.
#define INDENT_DBG_MEX(dbgLevel, curDbgLevel, mex)
We are producing a debug version of the program, so the message is printed;.
refcount< structural_type_descriptor > structural_type_descriptorRef
RefCount type definition of the structural_type_descriptor class structure.
File containing functions and utilities to support the printing of debug messagges.
This step adds the current module to the technology library.
This file contains the structures needed to manage a graph that will represent the state transition g...
Structure representing the most relevant information about the type of a structural object...
const ParameterConstRef Param
class containing all the parameters
#define GET_CLASS(obj)
Macro returning the actual type of an object.
#define STR_CST_taste_memory_enabling
The suffix of the memory enabling function.
std::string get_function_name() const
Return the name of the function.
Class to generate interface for taste architecture.
#define UUDATA_CONVERTER_STD
TasteInterfaceGeneration(const ParameterConstRef Param, const HLS_managerRef HLSMgr, unsigned int funId, const DesignFlowManagerConstRef design_flow_manager)
Constructor.
void set_owner(const structural_objectRef new_owner)
set the owner of the structural object
RelationshipType
The relationship type.
Source must be executed to satisfy target.
const unsigned int funId
identifier of the function to be processed (0 means that it is a global step)
#define STR_CST_taste_output_multiplexer
The suffix of the output multiplexer function.
This class manages the circuit structures.
const HLS_deviceRef HLS_D
reference to the information representing the target for the synthesis
virtual structural_objectRef find_member(const std::string &id, so_kind type, const structural_objectRef owner) const =0
Return the object named id of a given type which belongs to or it is associated with the object...
#define LIBRARY_STD_FU
standard library where all standard HLS resources are defined
Class specification of the manager of the technology library data structures.
static std::string ComputeSignature(const HLSFlowStep_Type hls_flow_step_type, const HLSFlowStepSpecializationConstRef hls_flow_step_specialization, const unsigned int function_id)
Compute the signature of a hls flow step.
void ComputeRelationships(DesignFlowStepSet &design_flow_step_set, const DesignFlowStep::RelationshipType relationship_type) override
Compute the relationships of a step with other steps.
~TasteInterfaceGeneration() override
Destructor.
#define STR(s)
Macro which performs a lexical_cast to a string.
Auxiliary methods for manipulating string.
virtual void AddParameter(const std::string &name, const std::string &default_value)
Add a parameter.
#define CLOCK_PORT_NAME
standard name for ports
structural_managerRef top
Store the top description.
bool HasToBeExecuted() const override
Check if this step has actually to be executed.
#define THROW_UNREACHABLE(str_expr)
helper function used to specify that some points should never be reached
Factory for hls flow step.
const CustomUnorderedSet< std::tuple< HLSFlowStep_Type, HLSFlowStepSpecializationConstRef, HLSFlowStep_Relationship > > ComputeHLSRelationships(const DesignFlowStep::RelationshipType relationship_type) const override
Return the set of analyses in relationship with this design step.
Class specification of the data structures used to manage technology information. ...
const std::string get_path() const
Return a unique identifier of the structural object.
static bool resize_if_busport(unsigned long long bus_size_bitsize, unsigned long long bus_addr_bitsize, unsigned long long bus_data_bitsize, unsigned long long bus_tag_bitsize, structural_objectRef port)
auxiliary function used to resize the bus ports with respect to their associated bus size ...
Classes to describe design flow graph.
Target must be reexecuted.
#define STR_CST_taste_reg_status
The suffix of the reg_status value computation function.
redefinition of set to manage ordered/unordered structures
#define ARRAY_1D_STD_BRAM_NN
utility function used to read files.
const Wrefcount< const DesignFlowManager > design_flow_manager
The design flow manager.
void set_black_box(bool bb)
Set the black box property associated with the structural_object.
void SetParameter(const std::string &name, const std::string &value)
Set a parameter value.
const BehavioralHelperConstRef CGetBehavioralHelper() const
Returns the helper associated with the function.
virtual enum so_kind get_kind() const =0
Virtual function used to find the real type of a structural_object instance.
const ParameterConstRef parameters
Set of input parameters.
DesignFlowStep_Status
The status of a step.
#define STR_CST_taste_endianess_check
The suffix of the endianess check function.
#define STR_CST_taste_data_size
The suffix of the data size function.
refcount< structural_manager > structural_managerRef
RefCount type definition of the structural_manager class structure.
#define STR_CST_taste_endianess_inversion
The suffix of the endianess inversion function.
DesignFlowStepFactoryConstRef CGetDesignFlowStepFactory() const final
Return the factory to create this type of steps.
#define GET_TYPE_SIZE(structural_obj)
Macro returning the size of the type of a structural object.
refcount< T > lock() const
This class describes all classes used to represent a structural object.
#define STR_CST_taste_address_translation
The suffix of the address translation function.
std::string GetPath(std::filesystem::path path)
void set_id(const std::string &s)
Set the identifier associated with the structural_object.
const CustomUnorderedSet< std::tuple< HLSFlowStep_Type, HLSFlowStepSpecializationConstRef, HLSFlowStep_Relationship > > ComputeHLSRelationships(const DesignFlowStep::RelationshipType relationship_type) const override
Return the set of analyses in relationship with this design step.
void AddSignal(const structural_managerRef SM, const structural_objectRef component1, const std::string &port1, const structural_objectRef component2, const std::string &port2, const std::string &signal_name)
Connects two ports by adding a signal.
#define WORK_LIBRARY
working library.
void AddConstant(const structural_managerRef SM, const structural_objectRef component, const std::string &port, const std::string &constant, const unsigned long long size)
Connects a constant to a port.
hlsRef HLS
HLS data structure of the function to be analyzed.
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
DesignFlowStep_Status InternalExec() override
Execute the step.
this class is used to manage the command-line or XML options.
Class implementation of the structural_manager.
int debug_level
The debug level.
refcount< const HLSFlowStepSpecialization > HLSFlowStepSpecializationConstRef
const refcount definition of the class
Information about speciaization of add_library.
void AddConnection(const structural_managerRef SM, const structural_objectRef component1, const std::string &port1, const structural_objectRef component2, const std::string &port2)
Connects two ports by adding a signal.
#define register_SE
register with synchronous enable
Class generating minimal interfaces.
void add_sign_vector(const structural_managerRef SM, const structural_objectRef sig1, const structural_objectRef sig2, const std::string &sig_name)
Connects two ports by adding a vector signal (i.e., wire)
Data structure definition for high-level synthesis flow.
#define NULL_VERTEX
null vertex definition
Datastructure to represent memory information in high-level synthesis.
Class specification of the manager of the tree structures extracted from the raw file.
HLS specialization of generic_device.
std::string get_library(const std::string &Name) const
Return the higher priority library where the given component is stored.
#define THROW_ASSERT(cond, str_expr)
helper function used to check an assert and if needed to throw an error in a standard way ...