PandA-2024.02
PrintfCSModuleGenerator.cpp
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1 /*
2  *
3  * _/_/_/ _/_/ _/ _/ _/_/_/ _/_/
4  * _/ _/ _/ _/ _/_/ _/ _/ _/ _/ _/
5  * _/_/_/ _/_/_/_/ _/ _/_/ _/ _/ _/_/_/_/
6  * _/ _/ _/ _/ _/ _/ _/ _/ _/
7  * _/ _/ _/ _/ _/ _/_/_/ _/ _/
8  *
9  * ***********************************************
10  * PandA Project
11  * URL: http://panda.dei.polimi.it
12  * Politecnico di Milano - DEIB
13  * System Architectures Group
14  * ***********************************************
15  * Copyright (C) 2022-2024 Politecnico di Milano
16  *
17  * This file is part of the PandA framework.
18  *
19  * The PandA framework is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 3 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27  * GNU General Public License for more details.
28  *
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30  * along with this program. If not, see <http://www.gnu.org/licenses/>.
31  *
32  */
46 #include "PrintfCSModuleGenerator.hpp"
47 
48 #include "hls_manager.hpp"
49 #include "language_writer.hpp"
50 #include "memory.hpp"
51 
52 PrintfCSModuleGenerator::PrintfCSModuleGenerator(const HLS_managerRef& _HLSMgr) : Registrar(_HLSMgr)
53 {
54 }
55 
56 void PrintfCSModuleGenerator::InternalExec(std::ostream& out, structural_objectRef /* mod */,
57  unsigned int /* function_id */, vertex /* op_v */,
58  const HDLWriter_Language /* language */,
59  const std::vector<ModuleGenerator::parameter>& _p,
60  const std::vector<ModuleGenerator::parameter>& /* _ports_in */,
61  const std::vector<ModuleGenerator::parameter>& /* _ports_out */,
62  const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
63 {
64  const auto data_bus_bitsize = STR(HLSMgr->Rmem->get_bus_data_bitsize());
65  const auto addr_bus_bitsize = STR(HLSMgr->get_address_bitsize());
66  const auto size_bus_bitsize = STR(HLSMgr->Rmem->get_bus_size_bitsize());
67 
68  const auto selector_dimension = STR(_p.size() < 2U ? 2U : _p.size());
69  const auto selector_left = STR(((_p.size() - 1U) < 1U) ? 1U : (_p.size() - 1U));
70 
71  std::string sensitivity;
72  for(auto i = 0U; i < _p.size(); i++)
73  {
74  sensitivity += " or " + _p[i].name;
75  }
76 
77  std::string case_statement;
78  if(_p.size() > 1)
79  {
80  case_statement = "case (_present_selector)\n";
81  for(auto i = 0U, selector = 1U; i < _p.size(); i++, selector *= 2)
82  {
83  case_statement += " " + selector_dimension + "'d" + STR(selector) +
84  ":\n"
85  " begin\n"
86  " data1=" +
87  _p[i].name +
88  ";\n"
89  " data1_size=BITSIZE_in" +
90  STR(i + 1) +
91  ";\n"
92  " end\n";
93  }
94  case_statement += " default:\n"
95  " begin\n"
96  " data1 = 64'b0;\n"
97  " data1_size = 8'b0;\n"
98  " end\n"
99  " endcase";
100  }
101  else
102  {
103  case_statement = "";
104  }
105 
106  const auto fsm =
107  ""
108  "// synthesis translate_off\n"
109  "function real bits32_to_real64;\n"
110  " input [31:0] fin1;\n"
111  " reg [7:0] exponent1;\n"
112  " reg is_exp_zero;\n"
113  " reg is_all_ones;\n"
114  " reg [10:0] exp_tmp;\n"
115  " reg [63:0] fout1;\n"
116  "begin\n"
117  " exponent1 = fin1[30:23];\n"
118  " is_exp_zero = exponent1 == 8'd0;\n"
119  " is_all_ones = exponent1 == {8{1'b1}};\n"
120  " exp_tmp = {3'd0, exponent1} + 11'd896;\n"
121  " fout1[63] = fin1[31];\n"
122  " fout1[62:52] = is_exp_zero ? 11'd0 : (is_all_ones ? {11{1'b1}} : exp_tmp);\n"
123  " fout1[51:29] = fin1[22:0];\n"
124  " fout1[28:0] = 29'd0;\n"
125  " bits32_to_real64 = $bitstoreal(fout1);\n"
126  "end\n"
127  "endfunction\n"
128  "// synthesis translate_on\n"
129  "reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer;\n"
130  "reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer;\n"
131  "reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer1;\n"
132  "reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer1;\n"
133  "reg mem_sel_LOAD;\n"
134  "reg start_memory_op;\n"
135  "wire mem_done_port;\n"
136  "reg done_port;\n"
137  "wire [" +
138  data_bus_bitsize +
139  "-1:0] mem_out1;\n"
140  "reg [" +
141  addr_bus_bitsize +
142  "-1:0] mem_in2;\n"
143  "reg [" +
144  size_bus_bitsize +
145  "-1:0] mem_in3;\n"
146  "mem_ctrl_kernel #(.TAG_MEM_REQ(0), .BITSIZE_in1(" +
147  data_bus_bitsize + "), .BITSIZE_in2(" + addr_bus_bitsize + "), .BITSIZE_in3(" + size_bus_bitsize +
148  "), .BITSIZE_out1(" + data_bus_bitsize +
149  "), .BITSIZE_Mout_oe_ram(BITSIZE_Mout_oe_ram), .BITSIZE_Mout_we_ram(BITSIZE_Mout_we_ram), "
150  ".BITSIZE_Mout_addr_ram(BITSIZE_Mout_addr_ram), .BITSIZE_Mout_data_ram_size(BITSIZE_Mout_data_ram_size), "
151  ".BITSIZE_Mout_Wdata_ram(BITSIZE_Mout_Wdata_ram), .BITSIZE_Mout_tag_ram(BITSIZE_Mout_tag_ram), "
152  ".BITSIZE_M_Rdata_ram(BITSIZE_M_Rdata_ram), .BITSIZE_M_DataRdy(BITSIZE_M_DataRdy), "
153  ".BITSIZE_Min_tag(BITSIZE_Min_tag), .BITSIZE_request_accepted(BITSIZE_request_accepted)) "
154  "mem_ctrl_kernel_instance (.clock(clock), .in1(0), .in2(mem_in2), .in3(mem_in3), .in4(1'b1), "
155  ".sel_LOAD(mem_sel_LOAD), .sel_STORE(1'b0), .done_port(mem_done_port), .out1(mem_out1), "
156  ".Mout_oe_ram(Mout_oe_ram), .Mout_we_ram(Mout_we_ram), .Mout_addr_ram(Mout_addr_ram), "
157  ".Mout_data_ram_size(Mout_data_ram_size), .Mout_Wdata_ram(Mout_Wdata_ram), .Mout_tag_ram(Mout_tag_ram), "
158  ".M_Rdata_ram(M_Rdata_ram), .M_DataRdy(M_DataRdy), .Min_tag(Min_tag), .request_accepted(request_accepted), "
159  ".start_port(start_memory_op));\n"
160  "\n"
161  "parameter [3:0] S_0 = 4'd0,\n"
162  " S_1 = 4'd1,\n"
163  " S_2 = 4'd2,\n"
164  " S_3 = 4'd3,\n"
165  " S_4 = 4'd4,\n"
166  " S_5 = 4'd5,\n"
167  " S_6 = 4'd6,\n"
168  " S_7 = 4'd7,\n"
169  " S_8 = 4'd8,\n"
170  " S_9 = 4'd9,\n"
171  " S_10 = 4'd10;\n"
172  "reg [3:0] _present_state;\n"
173  "reg [3:0] _next_state;\n"
174  "reg [" +
175  selector_left +
176  ":0] _present_selector;\n"
177  "reg [" +
178  selector_left +
179  ":0] _next_selector;\n"
180  "reg [63:0] data1;\n"
181  "reg [7:0] _present_data2;\n"
182  "reg [7:0] _next_data2;\n"
183  "reg [7:0] data1_size;\n"
184  "reg write_done;\n"
185  "\n"
186  " always @(posedge clock 1RESET_EDGE)\n"
187  " if (1RESET_VALUE)\n"
188  " begin\n"
189  " _present_state <= S_0;\n"
190  " _present_pointer <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
191  " _present_pointer1 <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
192  " _present_selector <=" +
193  selector_dimension +
194  "'d0;\n"
195  " _present_data2 <= 8'b0;\n"
196  " end\n"
197  " else\n"
198  " begin\n"
199  " _present_state <= _next_state;\n"
200  " _present_pointer <= _next_pointer;\n"
201  " _present_pointer1 <= _next_pointer1;\n"
202  " _present_selector <= _next_selector;\n"
203  " _present_data2 <= _next_data2;\n"
204  " end\n"
205  "\n"
206  " always @(_present_state or _present_pointer or _present_pointer1 or _present_selector or start_port or "
207  "M_DataRdy" +
208  sensitivity +
209  " or _present_data2 or mem_done_port or M_Rdata_ram[7:0])\n"
210  " begin\n"
211  " _next_state = _present_state;\n"
212  " _next_pointer = _present_pointer;\n"
213  " _next_pointer1 = _present_pointer1;\n"
214  " _next_selector = _present_selector;\n"
215  " _next_data2 = _present_data2;\n"
216  " done_port = 1'b0;\n"
217  " mem_sel_LOAD = 1'b0;\n"
218  " start_memory_op= 1'b0;\n"
219  " mem_in2=" +
220  addr_bus_bitsize +
221  "'d0;\n"
222  " mem_in3=" +
223  size_bus_bitsize +
224  "'d0;\n"
225  " " +
226  case_statement +
227  "\n"
228  " case (_present_state)\n"
229  " S_0:\n"
230  " if(start_port)\n"
231  " begin\n"
232  " _next_pointer=0;\n"
233  " _next_pointer1=0;\n"
234  " _next_state=S_1; \n"
235  " _next_selector=" +
236  selector_dimension +
237  "'d2;\n"
238  " end\n"
239  " \n"
240  " S_1:\n"
241  " begin\n"
242  " mem_in2 = in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer;\n"
243  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
244  " mem_sel_LOAD=1'b1;\n"
245  " start_memory_op= 1'b1;\n"
246  " if(mem_done_port)\n"
247  " begin\n"
248  " _next_data2 = mem_out1[7:0];\n"
249  " _next_state=S_2;\n"
250  " // synthesis translate_off\n"
251  " write_done=1'b0;\n"
252  " // synthesis translate_on\n"
253  " end\n"
254  " else\n"
255  " begin\n"
256  " _next_state=S_8;\n"
257  " end\n"
258  " end\n"
259  " S_8:\n"
260  " begin\n"
261  " mem_sel_LOAD=1'b1;\n"
262  " start_memory_op= 1'b0;\n"
263  " if(mem_done_port)\n"
264  " begin\n"
265  " _next_data2 = mem_out1[7:0];\n"
266  " _next_state=S_2;\n"
267  " // synthesis translate_off\n"
268  " write_done=1'b0;\n"
269  " // synthesis translate_on\n"
270  " end\n"
271  " else\n"
272  " begin\n"
273  " _next_state=S_8;\n"
274  " end\n"
275  " end\n"
276  " S_2:\n"
277  " begin\n"
278  " _next_pointer=_present_pointer+1'd1;\n"
279  " if((_present_data2!=8'd0)&&(_present_data2!=8'd37))\n"
280  " begin\n"
281  "// synthesis translate_off\n"
282  " if(!write_done)\n"
283  " begin\n"
284  " $write(\"%c\",_present_data2);\n"
285  " write_done=1'b1;\n"
286  " end\n"
287  "// synthesis translate_on\n"
288  " _next_state=S_1;\n"
289  " end\n"
290  " else if(_present_data2==8'd37)\n"
291  " _next_state=S_3;\n"
292  " else if(_present_data2==8'd0)\n"
293  " begin\n"
294  " done_port = 1'b1;\n"
295  " _next_state=S_0;\n"
296  " end\n"
297  " end\n"
298  " S_3:\n"
299  " begin\n"
300  " mem_in2 = in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer;\n"
301  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
302  " mem_sel_LOAD=1'b1;\n"
303  " start_memory_op= 1'b1;\n"
304  " if(mem_done_port)\n"
305  " begin\n"
306  " _next_data2 = mem_out1[7:0];\n"
307  " _next_state=S_5;\n"
308  " // synthesis translate_off\n"
309  " write_done=1'b0;\n"
310  " // synthesis translate_on\n"
311  " end\n"
312  " else\n"
313  " begin\n"
314  " _next_state=S_9;\n"
315  " end\n"
316  " end\n"
317  " S_9:\n"
318  " begin\n"
319  " mem_sel_LOAD=1'b1;\n"
320  " if(mem_done_port)\n"
321  " begin\n"
322  " _next_data2 = mem_out1[7:0];\n"
323  " _next_state=S_5;\n"
324  " // synthesis translate_off\n"
325  " write_done=1'b0;\n"
326  " // synthesis translate_on\n"
327  " end\n"
328  " else\n"
329  " begin\n"
330  " _next_state=S_9;\n"
331  " end\n"
332  " end\n"
333  " S_5 :\n"
334  " begin\n"
335  " _next_state=S_6;\n"
336  " _next_pointer=_present_pointer+1'd1;\n"
337  " case(_present_data2)\n"
338  " 8'd37: //%%\n"
339  " begin\n"
340  " _next_state=S_1;\n"
341  "// synthesis translate_off\n"
342  " if(!write_done)\n"
343  " begin\n"
344  " $write(\"%c\",8'd37);\n"
345  " write_done=1'b1;\n"
346  " end\n"
347  "// synthesis translate_on\n"
348  " end\n"
349  " 8'd99: //Char\n"
350  " begin\n"
351  "// synthesis translate_off\n"
352  " if(!write_done)\n"
353  " begin\n"
354  " $write(\"%c\",data1[7:0]);\n"
355  " write_done=1'b1;\n"
356  " end\n"
357  "// synthesis translate_on\n"
358  " end\n"
359  " 8'd100: //Decimal %d\n"
360  " if(data1_size ==8'd64)\n"
361  " begin\n"
362  "// synthesis translate_off\n"
363  " if(!write_done)\n"
364  " begin\n"
365  " $write(\"%0d\",$signed(data1));\n"
366  " write_done=1'b1;\n"
367  " end\n"
368  "// synthesis translate_on\n"
369  " end\n"
370  " else if(data1_size ==8'd32)\n"
371  " begin\n"
372  "// synthesis translate_off\n"
373  " if(!write_done)\n"
374  " begin\n"
375  " $write(\"%0d\",$signed(data1[31:0]));\n"
376  " write_done=1'b1;\n"
377  " end\n"
378  "// synthesis translate_on\n"
379  " end\n"
380  " else if(data1_size ==8'd16)\n"
381  " begin\n"
382  "// synthesis translate_off\n"
383  " if(!write_done)\n"
384  " begin\n"
385  " $write(\"%0d\",$signed(data1[15:0]));\n"
386  " write_done=1'b1;\n"
387  " end\n"
388  "// synthesis translate_on\n"
389  " end\n"
390  " else if(data1_size ==8'd8)\n"
391  " begin\n"
392  "// synthesis translate_off\n"
393  " if(!write_done)\n"
394  " begin\n"
395  " $write(\"%0d\",$signed(data1[7:0]));\n"
396  " write_done=1'b1;\n"
397  " end\n"
398  "// synthesis translate_on\n"
399  " end\n"
400  " else\n"
401  " begin\n"
402  "// synthesis translate_off\n"
403  " $display(\"ERROR - Decimal precision not supported (d) %d\", data1_size);\n"
404  " $finish;\n"
405  "// synthesis translate_on\n"
406  " end\n"
407  " 8'd105: //Decimal %i\n"
408  " if(data1_size ==8'd64)\n"
409  " begin\n"
410  "// synthesis translate_off\n"
411  " if(!write_done)\n"
412  " begin\n"
413  " $write(\"%0d\",$signed(data1));\n"
414  " write_done=1'b1;\n"
415  " end\n"
416  "// synthesis translate_on\n"
417  " end\n"
418  " else if(data1_size ==8'd32)\n"
419  " begin\n"
420  "// synthesis translate_off\n"
421  " if(!write_done)\n"
422  " begin\n"
423  " $write(\"%0d\",$signed(data1[31:0]));\n"
424  " write_done=1'b1;\n"
425  " end\n"
426  "// synthesis translate_on\n"
427  " end\n"
428  " else if(data1_size ==8'd16)\n"
429  " begin\n"
430  "// synthesis translate_off\n"
431  " if(!write_done)\n"
432  " begin\n"
433  " $write(\"%0d\",$signed(data1[15:0]));\n"
434  " write_done=1'b1;\n"
435  " end\n"
436  "// synthesis translate_on\n"
437  " end\n"
438  " else if(data1_size ==8'd8)\n"
439  " begin\n"
440  "// synthesis translate_off\n"
441  " if(!write_done)\n"
442  " begin\n"
443  " $write(\"%0d\",$signed(data1[7:0]));\n"
444  " write_done=1'b1;\n"
445  " end\n"
446  "// synthesis translate_on\n"
447  " end\n"
448  " else\n"
449  " begin\n"
450  "// synthesis translate_off\n"
451  " $display(\"ERROR - Decimal precision not supported (i) %d\", data1_size);\n"
452  " $finish;\n"
453  "// synthesis translate_on\n"
454  " end\n"
455  " 8'd101: //Exponential %e\n"
456  " begin\n"
457  " if(data1_size ==8'd64)\n"
458  " begin\n"
459  "// synthesis translate_off\n"
460  " if(!write_done)\n"
461  " begin\n"
462  " $write(\"%e\",$bitstoreal(data1));\n"
463  " write_done=1'b1;\n"
464  " end\n"
465  "// synthesis translate_on\n"
466  " end\n"
467  " else if(data1_size ==8'd32)\n"
468  " begin\n"
469  "// synthesis translate_off\n"
470  " if(!write_done)\n"
471  " begin\n"
472  " $write(\"%e\",bits32_to_real64(data1[31:0]));\n"
473  " write_done=1'b1;\n"
474  " end\n"
475  "// synthesis translate_on\n"
476  " end\n"
477  " else\n"
478  " begin\n"
479  "// synthesis translate_off\n"
480  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
481  " $finish;\n"
482  "// synthesis translate_on\n"
483  " end\n"
484  " end\n"
485  " 8'd69: //Exponential %E\n"
486  " begin\n"
487  " if(data1_size ==8'd64)\n"
488  " begin\n"
489  "// synthesis translate_off\n"
490  " if(!write_done)\n"
491  " begin\n"
492  " $write(\"%e\",$bitstoreal(data1));\n"
493  " write_done=1'b1;\n"
494  " end\n"
495  "// synthesis translate_on\n"
496  " end\n"
497  " else if(data1_size ==8'd32)\n"
498  " begin\n"
499  "// synthesis translate_off\n"
500  " if(!write_done)\n"
501  " begin\n"
502  " $write(\"%e\",bits32_to_real64(data1[31:0]));\n"
503  " write_done=1'b1;\n"
504  " end\n"
505  "// synthesis translate_on\n"
506  " end\n"
507  " else\n"
508  " begin\n"
509  "// synthesis translate_off\n"
510  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
511  " $finish;\n"
512  "// synthesis translate_on\n"
513  " end\n"
514  " end\n"
515  " 8'd102: //Float %f\n"
516  " begin\n"
517  " if(data1_size==8'd64)\n"
518  " begin\n"
519  "// synthesis translate_off\n"
520  " if(!write_done)\n"
521  " begin\n"
522  " $write(\"%20.20f\",$bitstoreal(data1));\n"
523  " write_done=1'b1;\n"
524  " end\n"
525  "// synthesis translate_on\n"
526  " end\n"
527  " else if(data1_size ==8'd32)\n"
528  " begin\n"
529  "// synthesis translate_off\n"
530  " if(!write_done)\n"
531  " begin\n"
532  " $write(\"%20.20f\",bits32_to_real64(data1[31:0]));\n"
533  " write_done=1'b1;\n"
534  " end\n"
535  "// synthesis translate_on\n"
536  " end\n"
537  " else\n"
538  " begin\n"
539  "// synthesis translate_off\n"
540  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
541  " $finish;\n"
542  "// synthesis translate_on\n"
543  " end\n"
544  " end\n"
545  " 8'd70: //Float %F\n"
546  " begin\n"
547  " if(data1_size==8'd64)\n"
548  " begin\n"
549  "// synthesis translate_off\n"
550  " if(!write_done)\n"
551  " begin\n"
552  " $write(\"%20.20f\",$bitstoreal(data1));\n"
553  " write_done=1'b1;\n"
554  " end\n"
555  "// synthesis translate_on\n"
556  " end\n"
557  " else if(data1_size ==8'd32)\n"
558  " begin\n"
559  "// synthesis translate_off\n"
560  " if(!write_done)\n"
561  " begin\n"
562  " $write(\"%20.20f\",bits32_to_real64(data1[31:0]));\n"
563  " write_done=1'b1;\n"
564  " end\n"
565  "// synthesis translate_on\n"
566  " end\n"
567  " else\n"
568  " begin\n"
569  "// synthesis translate_off\n"
570  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
571  " $finish;\n"
572  "// synthesis translate_on\n"
573  " end\n"
574  " end\n"
575  " 8'd103: //Float %g\n"
576  " begin\n"
577  " if(data1_size==8'd64)\n"
578  " begin\n"
579  "// synthesis translate_off\n"
580  " if(!write_done)\n"
581  " begin\n"
582  " $write(\"%20.20g\",$bitstoreal(data1));\n"
583  " write_done=1'b1;\n"
584  " end\n"
585  "// synthesis translate_on\n"
586  " end\n"
587  " else if(data1_size ==8'd32)\n"
588  " begin\n"
589  "// synthesis translate_off\n"
590  " if(!write_done)\n"
591  " begin\n"
592  " $write(\"%20.20g\",bits32_to_real64(data1[31:0]));\n"
593  " write_done=1'b1;\n"
594  " end\n"
595  "// synthesis translate_on\n"
596  " end\n"
597  " else\n"
598  " begin\n"
599  "// synthesis translate_off\n"
600  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
601  " $finish;\n"
602  "// synthesis translate_on\n"
603  " end\n"
604  " end\n"
605  " 8'd71: //Float %G\n"
606  " begin\n"
607  " if(data1_size==8'd64)\n"
608  " begin\n"
609  "// synthesis translate_off\n"
610  " if(!write_done)\n"
611  " begin\n"
612  " $write(\"%20.20g\",$bitstoreal(data1));\n"
613  " write_done=1'b1;\n"
614  " end\n"
615  "// synthesis translate_on\n"
616  " end\n"
617  " else if(data1_size ==8'd32)\n"
618  " begin\n"
619  "// synthesis translate_off\n"
620  " if(!write_done)\n"
621  " begin\n"
622  " $write(\"%20.20g\",bits32_to_real64(data1[31:0]));\n"
623  " write_done=1'b1;\n"
624  " end\n"
625  "// synthesis translate_on\n"
626  " end\n"
627  " else\n"
628  " begin\n"
629  "// synthesis translate_off\n"
630  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
631  " $finish;\n"
632  "// synthesis translate_on\n"
633  " end\n"
634  " end\n"
635  " 8'd111: //Octal\n"
636  " if(data1_size ==8'd64)\n"
637  " begin\n"
638  "// synthesis translate_off\n"
639  " if(!write_done)\n"
640  " begin\n"
641  " $write(\"%0o\",data1);\n"
642  " write_done=1'b1;\n"
643  " end\n"
644  "// synthesis translate_on\n"
645  " end\n"
646  " else if(data1_size ==8'd32)\n"
647  " begin\n"
648  "// synthesis translate_off\n"
649  " if(!write_done)\n"
650  " begin\n"
651  " $write(\"%0o\",data1[31:0]);\n"
652  " write_done=1'b1;\n"
653  " end\n"
654  "// synthesis translate_on\n"
655  " end\n"
656  " else if(data1_size ==8'd16)\n"
657  " begin\n"
658  "// synthesis translate_off\n"
659  " if(!write_done)\n"
660  " begin\n"
661  " $write(\"%0o\",data1[15:0]);\n"
662  " write_done=1'b1;\n"
663  " end\n"
664  "// synthesis translate_on\n"
665  " end\n"
666  " else if(data1_size ==8'd8)\n"
667  " begin\n"
668  "// synthesis translate_off\n"
669  " if(!write_done)\n"
670  " begin\n"
671  " $write(\"%0o\",data1[7:0]);\n"
672  " write_done=1'b1;\n"
673  " end\n"
674  "// synthesis translate_on\n"
675  " end\n"
676  " else\n"
677  " begin\n"
678  "// synthesis translate_off\n"
679  " $display(\"ERROR - Octal precision not supported %d\", data1_size);\n"
680  " $finish;\n"
681  "// synthesis translate_on\n"
682  " end\n"
683  " 8'd112: //%p\n"
684  " begin\n"
685  "// synthesis translate_off\n"
686  " if(!write_done)\n"
687  " begin\n"
688  " $write(\"0x%0h\",data1);\n"
689  " write_done=1'b1;\n"
690  " end\n"
691  "// synthesis translate_on\n"
692  " end\n"
693  " 8'd115: //String\n"
694  " begin\n"
695  " _next_state=S_7;\n"
696  " _next_pointer1=0;\n"
697  " end\n"
698  " 8'd117: //unsigned int %u TO BE FIXED\n"
699  " if(data1_size ==8'd64)\n"
700  " begin\n"
701  "// synthesis translate_off\n"
702  " if(!write_done)\n"
703  " begin\n"
704  " $write(\"%0d\",$unsigned(data1));\n"
705  " write_done=1'b1;\n"
706  " end\n"
707  "// synthesis translate_on\n"
708  " end\n"
709  " else if(data1_size ==8'd32)\n"
710  " begin\n"
711  "// synthesis translate_off\n"
712  " if(!write_done)\n"
713  " begin\n"
714  " $write(\"%0d\",$unsigned(data1[31:0]));\n"
715  " write_done=1'b1;\n"
716  " end\n"
717  "// synthesis translate_on\n"
718  " end\n"
719  " else if(data1_size ==8'd16)\n"
720  " begin\n"
721  "// synthesis translate_off\n"
722  " if(!write_done)\n"
723  " begin\n"
724  " $write(\"%0d\",$unsigned(data1[15:0]));\n"
725  " write_done=1'b1;\n"
726  " end\n"
727  "// synthesis translate_on\n"
728  " end\n"
729  " else if(data1_size ==8'd8)\n"
730  " begin\n"
731  "// synthesis translate_off\n"
732  " if(!write_done)\n"
733  " begin\n"
734  " $write(\"%0d\",$unsigned(data1[7:0]));\n"
735  " write_done=1'b1;\n"
736  " end\n"
737  "// synthesis translate_on\n"
738  " end\n"
739  " else\n"
740  " begin\n"
741  "// synthesis translate_off\n"
742  " $display(\"ERROR - Unsigned precision not supported %d\", data1_size);\n"
743  " $finish;\n"
744  "// synthesis translate_on\n"
745  " end\n"
746  " 8'd120: //Hex %x\n"
747  " if(data1_size ==8'd64)\n"
748  " begin\n"
749  "// synthesis translate_off\n"
750  " if(!write_done)\n"
751  " begin\n"
752  " $write(\"%0h\",data1);\n"
753  " write_done=1'b1;\n"
754  " end\n"
755  "// synthesis translate_on\n"
756  " end\n"
757  " else if(data1_size ==8'd32)\n"
758  " begin\n"
759  "// synthesis translate_off\n"
760  " if(!write_done)\n"
761  " begin\n"
762  " $write(\"%0h\",data1[31:0]);\n"
763  " write_done=1'b1;\n"
764  " end\n"
765  "// synthesis translate_on\n"
766  " end\n"
767  " else if(data1_size ==8'd16)\n"
768  " begin\n"
769  "// synthesis translate_off\n"
770  " if(!write_done)\n"
771  " begin\n"
772  " $write(\"%0h\",data1[15:0]);\n"
773  " write_done=1'b1;\n"
774  " end\n"
775  "// synthesis translate_on\n"
776  " end\n"
777  " else if(data1_size ==8'd8)\n"
778  " begin\n"
779  "// synthesis translate_off\n"
780  " if(!write_done)\n"
781  " begin\n"
782  " $write(\"%0h\",data1[7:0]);\n"
783  " write_done=1'b1;\n"
784  " end\n"
785  "// synthesis translate_on\n"
786  " end\n"
787  " else\n"
788  " begin\n"
789  "// synthesis translate_off\n"
790  " $display(\"ERROR - Hex precision not supported %d\", data1_size);\n"
791  " $finish;\n"
792  "// synthesis translate_on\n"
793  " end\n"
794  " 8'd88: //Hex %X\n"
795  " if(data1_size ==8'd64)\n"
796  " begin\n"
797  "// synthesis translate_off\n"
798  " if(!write_done)\n"
799  " begin\n"
800  " $write(\"%0h\",data1);\n"
801  " write_done=1'b1;\n"
802  " end\n"
803  "// synthesis translate_on\n"
804  " end\n"
805  " else if(data1_size ==8'd32)\n"
806  " begin\n"
807  "// synthesis translate_off\n"
808  " if(!write_done)\n"
809  " begin\n"
810  " $write(\"%0h\",data1[31:0]);\n"
811  " write_done=1'b1;\n"
812  " end\n"
813  "// synthesis translate_on\n"
814  " end\n"
815  " else if(data1_size ==8'd16)\n"
816  " begin\n"
817  "// synthesis translate_off\n"
818  " if(!write_done)\n"
819  " begin\n"
820  " $write(\"%0h\",data1[15:0]);\n"
821  " write_done=1'b1;\n"
822  " end\n"
823  "// synthesis translate_on\n"
824  " end\n"
825  " else if(data1_size ==8'd8)\n"
826  " begin\n"
827  "// synthesis translate_off\n"
828  " if(!write_done)\n"
829  " begin\n"
830  " $write(\"%0h\",data1[7:0]);\n"
831  " write_done=1'b1;\n"
832  " end\n"
833  "// synthesis translate_on\n"
834  " end\n"
835  " else\n"
836  " begin\n"
837  "// synthesis translate_off\n"
838  " $display(\"ERROR - Hex precision not supported %d\", data1_size);\n"
839  " $finish;\n"
840  "// synthesis translate_on\n"
841  " end\n"
842  " default:\n"
843  " _next_state=S_3;\n"
844  " endcase\n"
845  " end\n"
846  " S_6:\n"
847  " begin\n"
848  " _next_selector=_present_selector<<1;\n"
849  " _next_state=S_1;\n"
850  " end\n"
851  " S_7:\n"
852  " begin\n"
853  " mem_in2 = data1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer1;\n"
854  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
855  " mem_sel_LOAD=1'b1;\n"
856  " start_memory_op= 1'b1;\n"
857  " if(mem_done_port)\n"
858  " begin\n"
859  " _next_data2 = mem_out1[7:0];\n"
860  " _next_state=S_4;\n"
861  "// synthesis translate_off\n"
862  " write_done=1'b0;\n"
863  "// synthesis translate_on\n"
864  " end\n"
865  " else\n"
866  " begin\n"
867  " _next_state=S_10;\n"
868  " end\n"
869  " end\n"
870  " S_10:\n"
871  " begin\n"
872  " mem_sel_LOAD=1'b1;\n"
873  " if(mem_done_port)\n"
874  " begin\n"
875  " _next_data2 = mem_out1[7:0];\n"
876  " _next_state=S_4;\n"
877  " // synthesis translate_off\n"
878  " write_done=1'b0;\n"
879  " // synthesis translate_on\n"
880  " end\n"
881  " else\n"
882  " begin\n"
883  " _next_state=S_10;\n"
884  " end\n"
885  " end\n"
886  " S_4:\n"
887  " begin\n"
888  " _next_pointer1=_present_pointer1+1'd1;\n"
889  " if(_present_data2!=8'd0)\n"
890  " begin\n"
891  "// synthesis translate_off\n"
892  " if(!write_done)\n"
893  " begin\n"
894  " $write(\"%c\",_present_data2);\n"
895  " write_done=1'b1;\n"
896  " end\n"
897  "// synthesis translate_on\n"
898  " _next_state=S_7;\n"
899  " end\n"
900  " else\n"
901  " _next_state=S_6;\n"
902  " end\n"
903  " endcase\n"
904  " end\n";
905 
906  out << fsm;
907 }
hls_manager.hpp
Data structure representing the entire HLS information.
PrintfCSModuleGenerator::PrintfCSModuleGenerator
PrintfCSModuleGenerator(const HLS_managerRef &HLSMgr)
Definition: PrintfCSModuleGenerator.cpp:52
PrintfCSModuleGenerator::InternalExec
void InternalExec(std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final
Definition: PrintfCSModuleGenerator.cpp:56
STR
#define STR(s)
Macro which performs a lexical_cast to a string.
Definition: string_manipulation.hpp:52
HDLWriter_Language
HDLWriter_Language
Definition: language_writer.hpp:78
language_writer.hpp
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
vertex
boost::graph_traits< graph >::vertex_descriptor vertex
vertex definition.
Definition: graph.hpp:1303
bit_lattice::U
refcount
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
memory.hpp
Datastructure to represent memory information in high-level synthesis.
Generated on Mon Feb 12 2024 13:02:54 for PandA-2024.02 by doxygen 1.8.13