PandA-2024.02
PrintfP1NModuleGenerator.cpp
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48 #include "PrintfP1NModuleGenerator.hpp"
49 
50 #include "hls_manager.hpp"
51 #include "language_writer.hpp"
52 #include "memory.hpp"
53 
54 PrintfP1NModuleGenerator::PrintfP1NModuleGenerator(const HLS_managerRef& _HLSMgr) : Registrar(_HLSMgr)
55 {
56 }
57 
58 void PrintfP1NModuleGenerator::InternalExec(std::ostream& out, structural_objectRef /* mod */,
59  unsigned int /* function_id */, vertex /* op_v */,
60  const HDLWriter_Language /* language */,
61  const std::vector<ModuleGenerator::parameter>& _p,
62  const std::vector<ModuleGenerator::parameter>& /* _ports_in */,
63  const std::vector<ModuleGenerator::parameter>& /* _ports_out */,
64  const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
65 {
66  const auto data_bus_bitsize = STR(HLSMgr->Rmem->get_bus_data_bitsize());
67  const auto addr_bus_bitsize = STR(HLSMgr->get_address_bitsize());
68  const auto size_bus_bitsize = STR(HLSMgr->Rmem->get_bus_size_bitsize());
69 
70  const auto selector_dimension = STR(_p.size() < 2U ? 2U : _p.size());
71  const auto selector_left = STR(((_p.size() - 1U) < 1U) ? 1U : (_p.size() - 1U));
72 
73  std::string sensitivity;
74  for(auto i = 0U; i < _p.size(); i++)
75  {
76  sensitivity += " or " + _p[i].name;
77  }
78 
79  std::string case_statement;
80  if(_p.size() > 1)
81  {
82  case_statement = "case (_present_selector)\n";
83  for(auto i = 0U, selector = 1U; i < _p.size(); i++, selector *= 2)
84  {
85  case_statement += " " + selector_dimension + "'d" + STR(selector) +
86  ":\n"
87  " begin\n"
88  " data1=" +
89  _p[i].name +
90  ";\n"
91  " data1_size=BITSIZE_in" +
92  STR(i + 1) +
93  ";\n"
94  " end\n";
95  }
96  case_statement += " default:\n"
97  " begin\n"
98  " data1 = 64'b0;\n"
99  " data1_size = 8'b0;\n"
100  " end\n"
101  " endcase";
102  }
103  else
104  {
105  case_statement = "";
106  }
107 
108  const auto fsm =
109  "// synthesis translate_off\n"
110  "function real bits32_to_real64;\n"
111  " input [31:0] fin1;\n"
112  " reg [7:0] exponent1;\n"
113  " reg is_exp_zero;\n"
114  " reg is_all_ones;\n"
115  " reg [10:0] exp_tmp;\n"
116  " reg [63:0] fout1;\n"
117  "begin\n"
118  " exponent1 = fin1[30:23];\n"
119  " is_exp_zero = exponent1 == 8'd0;\n"
120  " is_all_ones = exponent1 == {8{1'b1}};\n"
121  " exp_tmp = {3'd0, exponent1} + 11'd896;\n"
122  " fout1[63] = fin1[31];\n"
123  " fout1[62:52] = is_exp_zero ? 11'd0 : (is_all_ones ? {11{1'b1}} : exp_tmp);\n"
124  " fout1[51:29] = fin1[22:0];\n"
125  " fout1[28:0] = 29'd0;\n"
126  " bits32_to_real64 = $bitstoreal(fout1);\n"
127  "end\n"
128  "endfunction\n"
129  "// synthesis translate_on\n"
130  "reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer;\n"
131  "reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer;\n"
132  "reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer1;\n"
133  "reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer1;\n"
134  "reg mem_sel_LOAD;\n"
135  "wire mem_done_port;\n"
136  "reg done_port;\n"
137  "reg mem_start_port;\n"
138  "wire [" +
139  data_bus_bitsize +
140  "-1:0] mem_out1;\n"
141  "reg [" +
142  addr_bus_bitsize +
143  "-1:0] mem_in2;\n"
144  "reg [" +
145  size_bus_bitsize +
146  "-1:0] mem_in3;\n"
147  " MEMORY_CTRL_P1N #(.BITSIZE_in1(" +
148  data_bus_bitsize + "), .BITSIZE_in2(" + addr_bus_bitsize + "), .BITSIZE_in3(" + size_bus_bitsize +
149  "), .BITSIZE_in4(1), .BITSIZE_out1(" + data_bus_bitsize +
150  "), .BITSIZE_Min_oe_ram(BITSIZE_Min_oe_ram), .PORTSIZE_Min_oe_ram(PORTSIZE_Min_oe_ram), "
151  ".BITSIZE_Min_we_ram(BITSIZE_Min_we_ram), .PORTSIZE_Min_we_ram(PORTSIZE_Min_we_ram), "
152  ".BITSIZE_Mout_oe_ram(BITSIZE_Mout_oe_ram), .PORTSIZE_Mout_oe_ram(PORTSIZE_Mout_oe_ram), "
153  ".BITSIZE_Mout_we_ram(BITSIZE_Mout_we_ram), .PORTSIZE_Mout_we_ram(PORTSIZE_Mout_we_ram), "
154  ".BITSIZE_M_DataRdy(BITSIZE_M_DataRdy), .PORTSIZE_M_DataRdy(PORTSIZE_M_DataRdy), "
155  ".BITSIZE_Min_addr_ram(BITSIZE_Min_addr_ram), .PORTSIZE_Min_addr_ram(PORTSIZE_Min_addr_ram), "
156  ".BITSIZE_Mout_addr_ram(BITSIZE_Mout_addr_ram), .PORTSIZE_Mout_addr_ram(PORTSIZE_Mout_addr_ram), "
157  ".BITSIZE_M_Rdata_ram(BITSIZE_M_Rdata_ram), .PORTSIZE_M_Rdata_ram(PORTSIZE_M_Rdata_ram), "
158  ".BITSIZE_Min_Wdata_ram(BITSIZE_Min_Wdata_ram), .PORTSIZE_Min_Wdata_ram(PORTSIZE_Min_Wdata_ram), "
159  ".BITSIZE_Mout_Wdata_ram(BITSIZE_Mout_Wdata_ram), .PORTSIZE_Mout_Wdata_ram(PORTSIZE_Mout_Wdata_ram), "
160  ".BITSIZE_Min_data_ram_size(BITSIZE_Min_data_ram_size), "
161  ".PORTSIZE_Min_data_ram_size(PORTSIZE_Min_data_ram_size), "
162  ".BITSIZE_Mout_data_ram_size(BITSIZE_Mout_data_ram_size), "
163  ".PORTSIZE_Mout_data_ram_size(PORTSIZE_Mout_data_ram_size), .BITSIZE_access_allowed(BITSIZE_access_allowed), "
164  ".PORTSIZE_access_allowed(PORTSIZE_access_allowed), .BITSIZE_access_request(BITSIZE_access_request), "
165  ".PORTSIZE_access_request(PORTSIZE_access_request)) MEMORY_CTRL_P1N_instance (.done_port(mem_done_port), "
166  ".out1(mem_out1), .Mout_oe_ram(Mout_oe_ram), .Mout_we_ram(Mout_we_ram), .Mout_addr_ram(Mout_addr_ram), "
167  ".Mout_Wdata_ram(Mout_Wdata_ram), .Mout_data_ram_size(Mout_data_ram_size), .access_request(access_request), "
168  ".clock(clock), .start_port(mem_start_port), .in1(0), .in2(mem_in2), .in3(mem_in3), .in4(1), "
169  ".sel_LOAD(mem_sel_LOAD), .sel_STORE(1'b0), .Min_oe_ram(Min_oe_ram), .Min_we_ram(Min_we_ram), "
170  ".Min_addr_ram(Min_addr_ram), .M_Rdata_ram(M_Rdata_ram), .Min_Wdata_ram(Min_Wdata_ram), "
171  ".Min_data_ram_size(Min_data_ram_size), .M_DataRdy(M_DataRdy), .access_allowed(access_allowed));\n"
172  "\n"
173  "parameter [2:0] S_0 = 3'd0,\n"
174  " S_1 = 3'd1,\n"
175  " S_2 = 3'd2,\n"
176  " S_3 = 3'd3,\n"
177  " S_4 = 3'd4,\n"
178  " S_5 = 3'd5,\n"
179  " S_6 = 3'd6,\n"
180  " S_7 = 3'd7;\n"
181  "reg [2:0] _present_state;\n"
182  "reg [2:0] _next_state;\n"
183  "reg [" +
184  selector_left +
185  ":0] _present_selector;\n"
186  "reg [" +
187  selector_left +
188  ":0] _next_selector;\n"
189  "reg [63:0] data1;\n"
190  "reg [7:0] _present_data2;\n"
191  "reg [7:0] _next_data2;\n"
192  "reg [7:0] data1_size;\n"
193  "reg write_done;\n"
194  "\n"
195  " always @(posedge clock 1RESET_EDGE)\n"
196  " if (1RESET_VALUE)\n"
197  " begin\n"
198  " _present_state <= S_0;\n"
199  " _present_pointer <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
200  " _present_pointer1 <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
201  " _present_selector <=" +
202  selector_dimension +
203  "'d0;\n"
204  " _present_data2 <= 8'b0;\n"
205  " end\n"
206  " else\n"
207  " begin\n"
208  " _present_state <= _next_state;\n"
209  " _present_pointer <= _next_pointer;\n"
210  " _present_pointer1 <= _next_pointer1;\n"
211  " _present_selector <= _next_selector;\n"
212  " _present_data2 <= _next_data2;\n"
213  " end\n"
214  "\n"
215  " always @(_present_state or _present_pointer or _present_pointer1 or _present_selector or start_port or "
216  "M_DataRdy[0] or Min_we_ram or Min_oe_ram or Min_Wdata_ram or Min_addr_ram or Min_data_ram_size" +
217  sensitivity +
218  " or _present_data2 or mem_done_port or M_Rdata_ram[7:0])\n"
219  " begin\n"
220  " _next_state = _present_state;\n"
221  " _next_pointer = _present_pointer;\n"
222  " _next_pointer1 = _present_pointer1;\n"
223  " _next_selector = _present_selector;\n"
224  " _next_data2 = _present_data2;\n"
225  " done_port = 1'b0;\n"
226  " mem_sel_LOAD = 1'b0;\n"
227  " mem_start_port = 1'b0;\n"
228  " mem_in2=" +
229  addr_bus_bitsize +
230  "'d0;\n"
231  " mem_in3=" +
232  size_bus_bitsize +
233  "'d0;\n"
234  " " +
235  case_statement +
236  "\n"
237  " case (_present_state)\n"
238  " S_0:\n"
239  " if(start_port)\n"
240  " begin\n"
241  " _next_pointer=0;\n"
242  " _next_pointer1=0;\n"
243  " _next_state=S_1; \n"
244  " _next_selector=" +
245  selector_dimension +
246  "'d2;\n"
247  " end\n"
248  " \n"
249  " S_1:\n"
250  " begin\n"
251  " mem_in2 = in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer;\n"
252  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
253  " mem_sel_LOAD=1'b1;\n"
254  " mem_start_port=1'b1;\n"
255  " if(mem_done_port)\n"
256  " begin\n"
257  " _next_data2 = mem_out1[7:0];\n"
258  " _next_state=S_2;\n"
259  "// synthesis translate_off\n"
260  " write_done=1'b0;\n"
261  "// synthesis translate_on\n"
262  " end\n"
263  " end\n"
264  " S_2:\n"
265  " begin\n"
266  " _next_pointer=_present_pointer+1'd1;\n"
267  " if((_present_data2!=8'd0)&&(_present_data2!=8'd37))\n"
268  " begin\n"
269  "// synthesis translate_off\n"
270  " if(!write_done)\n"
271  " begin\n"
272  " $write(\"%c\",_present_data2);\n"
273  " write_done=1'b1;\n"
274  " end\n"
275  "// synthesis translate_on\n"
276  " _next_state=S_1;\n"
277  " end\n"
278  " else if(_present_data2==8'd37)\n"
279  " _next_state=S_3;\n"
280  " else if(_present_data2==8'd0)\n"
281  " begin\n"
282  " done_port = 1'b1;\n"
283  " _next_state=S_0;\n"
284  " end\n"
285  " end\n"
286  " S_3:\n"
287  " begin\n"
288  " mem_in2 = in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer;\n"
289  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
290  " mem_sel_LOAD=1'b1;\n"
291  " if(mem_done_port)\n"
292  " begin\n"
293  " _next_data2 = mem_out1[7:0];\n"
294  " _next_state=S_5;\n"
295  "// synthesis translate_off\n"
296  " write_done=1'b0;\n"
297  "// synthesis translate_on\n"
298  " end\n"
299  " end\n"
300  " S_5 :\n"
301  " begin\n"
302  " _next_state=S_6;\n"
303  " _next_pointer=_present_pointer+1'd1;\n"
304  " case(_present_data2)\n"
305  " 8'd37: //%%\n"
306  " begin\n"
307  " _next_state=S_1;\n"
308  "// synthesis translate_off\n"
309  " if(!write_done)\n"
310  " begin\n"
311  " $write(\"%c\",8'd37);\n"
312  " write_done=1'b1;\n"
313  " end\n"
314  "// synthesis translate_on\n"
315  " end\n"
316  " 8'd99: //Char\n"
317  " begin\n"
318  "// synthesis translate_off\n"
319  " if(!write_done)\n"
320  " begin\n"
321  " $write(\"%c\",data1[7:0]);\n"
322  " write_done=1'b1;\n"
323  " end\n"
324  "// synthesis translate_on\n"
325  " end\n"
326  " 8'd100: //Decimal %d\n"
327  " if(data1_size ==8'd64)\n"
328  " begin\n"
329  "// synthesis translate_off\n"
330  " if(!write_done)\n"
331  " begin\n"
332  " $write(\"%0d\",$signed(data1));\n"
333  " write_done=1'b1;\n"
334  " end\n"
335  "// synthesis translate_on\n"
336  " end\n"
337  " else if(data1_size ==8'd32)\n"
338  " begin\n"
339  "// synthesis translate_off\n"
340  " if(!write_done)\n"
341  " begin\n"
342  " $write(\"%0d\",$signed(data1[31:0]));\n"
343  " write_done=1'b1;\n"
344  " end\n"
345  "// synthesis translate_on\n"
346  " end\n"
347  " else if(data1_size ==8'd16)\n"
348  " begin\n"
349  "// synthesis translate_off\n"
350  " if(!write_done)\n"
351  " begin\n"
352  " $write(\"%0d\",$signed(data1[15:0]));\n"
353  " write_done=1'b1;\n"
354  " end\n"
355  "// synthesis translate_on\n"
356  " end\n"
357  " else if(data1_size ==8'd8)\n"
358  " begin\n"
359  "// synthesis translate_off\n"
360  " if(!write_done)\n"
361  " begin\n"
362  " $write(\"%0d\",$signed(data1[7:0]));\n"
363  " write_done=1'b1;\n"
364  " end\n"
365  "// synthesis translate_on\n"
366  " end\n"
367  " else\n"
368  " begin\n"
369  "// synthesis translate_off\n"
370  " $display(\"ERROR - Decimal precision not supported (d) %d\", data1_size);\n"
371  " $finish;\n"
372  "// synthesis translate_on\n"
373  " end\n"
374  " 8'd105: //Decimal %i\n"
375  " if(data1_size ==8'd64)\n"
376  " begin\n"
377  "// synthesis translate_off\n"
378  " if(!write_done)\n"
379  " begin\n"
380  " $write(\"%0d\",$signed(data1));\n"
381  " write_done=1'b1;\n"
382  " end\n"
383  "// synthesis translate_on\n"
384  " end\n"
385  " else if(data1_size ==8'd32)\n"
386  " begin\n"
387  "// synthesis translate_off\n"
388  " if(!write_done)\n"
389  " begin\n"
390  " $write(\"%0d\",$signed(data1[31:0]));\n"
391  " write_done=1'b1;\n"
392  " end\n"
393  "// synthesis translate_on\n"
394  " end\n"
395  " else if(data1_size ==8'd16)\n"
396  " begin\n"
397  "// synthesis translate_off\n"
398  " if(!write_done)\n"
399  " begin\n"
400  " $write(\"%0d\",$signed(data1[15:0]));\n"
401  " write_done=1'b1;\n"
402  " end\n"
403  "// synthesis translate_on\n"
404  " end\n"
405  " else if(data1_size ==8'd8)\n"
406  " begin\n"
407  "// synthesis translate_off\n"
408  " if(!write_done)\n"
409  " begin\n"
410  " $write(\"%0d\",$signed(data1[7:0]));\n"
411  " write_done=1'b1;\n"
412  " end\n"
413  "// synthesis translate_on\n"
414  " end\n"
415  " else\n"
416  " begin\n"
417  "// synthesis translate_off\n"
418  " $display(\"ERROR - Decimal precision not supported (i) %d\", data1_size);\n"
419  " $finish;\n"
420  "// synthesis translate_on\n"
421  " end\n"
422  " 8'd101: //Exponential %e\n"
423  " begin\n"
424  " if(data1_size ==8'd64)\n"
425  " begin\n"
426  "// synthesis translate_off\n"
427  " if(!write_done)\n"
428  " begin\n"
429  " $write(\"%e\",$bitstoreal(data1));\n"
430  " write_done=1'b1;\n"
431  " end\n"
432  "// synthesis translate_on\n"
433  " end\n"
434  " else if(data1_size ==8'd32)\n"
435  " begin\n"
436  "// synthesis translate_off\n"
437  " if(!write_done)\n"
438  " begin\n"
439  " $write(\"%e\",bits32_to_real64(data1[31:0]));\n"
440  " write_done=1'b1;\n"
441  " end\n"
442  "// synthesis translate_on\n"
443  " end\n"
444  " else\n"
445  " begin\n"
446  "// synthesis translate_off\n"
447  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
448  " $finish;\n"
449  "// synthesis translate_on\n"
450  " end\n"
451  " end\n"
452  " 8'd69: //Exponential %E\n"
453  " begin\n"
454  " if(data1_size ==8'd64)\n"
455  " begin\n"
456  "// synthesis translate_off\n"
457  " if(!write_done)\n"
458  " begin\n"
459  " $write(\"%e\",$bitstoreal(data1));\n"
460  " write_done=1'b1;\n"
461  " end\n"
462  "// synthesis translate_on\n"
463  " end\n"
464  " else if(data1_size ==8'd32)\n"
465  " begin\n"
466  "// synthesis translate_off\n"
467  " if(!write_done)\n"
468  " begin\n"
469  " $write(\"%e\",bits32_to_real64(data1[31:0]));\n"
470  " write_done=1'b1;\n"
471  " end\n"
472  "// synthesis translate_on\n"
473  " end\n"
474  " else\n"
475  " begin\n"
476  "// synthesis translate_off\n"
477  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
478  " $finish;\n"
479  "// synthesis translate_on\n"
480  " end\n"
481  " end\n"
482  " 8'd102: //Float %f\n"
483  " begin\n"
484  " if(data1_size==8'd64)\n"
485  " begin\n"
486  "// synthesis translate_off\n"
487  " if(!write_done)\n"
488  " begin\n"
489  " $write(\"%20.20f\",$bitstoreal(data1));\n"
490  " write_done=1'b1;\n"
491  " end\n"
492  "// synthesis translate_on\n"
493  " end\n"
494  " else if(data1_size ==8'd32)\n"
495  " begin\n"
496  "// synthesis translate_off\n"
497  " if(!write_done)\n"
498  " begin\n"
499  " $write(\"%20.20f\",bits32_to_real64(data1[31:0]));\n"
500  " write_done=1'b1;\n"
501  " end\n"
502  "// synthesis translate_on\n"
503  " end\n"
504  " else\n"
505  " begin\n"
506  "// synthesis translate_off\n"
507  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
508  " $finish;\n"
509  "// synthesis translate_on\n"
510  " end\n"
511  " end\n"
512  " 8'd70: //Float %F\n"
513  " begin\n"
514  " if(data1_size==8'd64)\n"
515  " begin\n"
516  "// synthesis translate_off\n"
517  " if(!write_done)\n"
518  " begin\n"
519  " $write(\"%20.20f\",$bitstoreal(data1));\n"
520  " write_done=1'b1;\n"
521  " end\n"
522  "// synthesis translate_on\n"
523  " end\n"
524  " else if(data1_size ==8'd32)\n"
525  " begin\n"
526  "// synthesis translate_off\n"
527  " if(!write_done)\n"
528  " begin\n"
529  " $write(\"%20.20f\",bits32_to_real64(data1[31:0]));\n"
530  " write_done=1'b1;\n"
531  " end\n"
532  "// synthesis translate_on\n"
533  " end\n"
534  " else\n"
535  " begin\n"
536  "// synthesis translate_off\n"
537  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
538  " $finish;\n"
539  "// synthesis translate_on\n"
540  " end\n"
541  " end\n"
542  " 8'd103: //Float %g\n"
543  " begin\n"
544  " if(data1_size==8'd64)\n"
545  " begin\n"
546  "// synthesis translate_off\n"
547  " if(!write_done)\n"
548  " begin\n"
549  " $write(\"%20.20g\",$bitstoreal(data1));\n"
550  " write_done=1'b1;\n"
551  " end\n"
552  "// synthesis translate_on\n"
553  " end\n"
554  " else if(data1_size ==8'd32)\n"
555  " begin\n"
556  "// synthesis translate_off\n"
557  " if(!write_done)\n"
558  " begin\n"
559  " $write(\"%20.20g\",bits32_to_real64(data1[31:0]));\n"
560  " write_done=1'b1;\n"
561  " end\n"
562  "// synthesis translate_on\n"
563  " end\n"
564  " else\n"
565  " begin\n"
566  "// synthesis translate_off\n"
567  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
568  " $finish;\n"
569  "// synthesis translate_on\n"
570  " end\n"
571  " end\n"
572  " 8'd71: //Float %G\n"
573  " begin\n"
574  " if(data1_size==8'd64)\n"
575  " begin\n"
576  "// synthesis translate_off\n"
577  " if(!write_done)\n"
578  " begin\n"
579  " $write(\"%20.20g\",$bitstoreal(data1));\n"
580  " write_done=1'b1;\n"
581  " end\n"
582  "// synthesis translate_on\n"
583  " end\n"
584  " else if(data1_size ==8'd32)\n"
585  " begin\n"
586  "// synthesis translate_off\n"
587  " if(!write_done)\n"
588  " begin\n"
589  " $write(\"%20.20g\",bits32_to_real64(data1[31:0]));\n"
590  " write_done=1'b1;\n"
591  " end\n"
592  "// synthesis translate_on\n"
593  " end\n"
594  " else\n"
595  " begin\n"
596  "// synthesis translate_off\n"
597  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
598  " $finish;\n"
599  "// synthesis translate_on\n"
600  " end\n"
601  " end\n"
602  " 8'd111: //Octal\n"
603  " if(data1_size ==8'd64)\n"
604  " begin\n"
605  "// synthesis translate_off\n"
606  " if(!write_done)\n"
607  " begin\n"
608  " $write(\"%0o\",data1);\n"
609  " write_done=1'b1;\n"
610  " end\n"
611  "// synthesis translate_on\n"
612  " end\n"
613  " else if(data1_size ==8'd32)\n"
614  " begin\n"
615  "// synthesis translate_off\n"
616  " if(!write_done)\n"
617  " begin\n"
618  " $write(\"%0o\",data1[31:0]);\n"
619  " write_done=1'b1;\n"
620  " end\n"
621  "// synthesis translate_on\n"
622  " end\n"
623  " else if(data1_size ==8'd16)\n"
624  " begin\n"
625  "// synthesis translate_off\n"
626  " if(!write_done)\n"
627  " begin\n"
628  " $write(\"%0o\",data1[15:0]);\n"
629  " write_done=1'b1;\n"
630  " end\n"
631  "// synthesis translate_on\n"
632  " end\n"
633  " else if(data1_size ==8'd8)\n"
634  " begin\n"
635  "// synthesis translate_off\n"
636  " if(!write_done)\n"
637  " begin\n"
638  " $write(\"%0o\",data1[7:0]);\n"
639  " write_done=1'b1;\n"
640  " end\n"
641  "// synthesis translate_on\n"
642  " end\n"
643  " else\n"
644  " begin\n"
645  "// synthesis translate_off\n"
646  " $display(\"ERROR - Octal precision not supported %d\", data1_size);\n"
647  " $finish;\n"
648  "// synthesis translate_on\n"
649  " end\n"
650  " 8'd112: //%p\n"
651  " begin\n"
652  "// synthesis translate_off\n"
653  " if(!write_done)\n"
654  " begin\n"
655  " $write(\"0x%0h\",data1);\n"
656  " write_done=1'b1;\n"
657  " end\n"
658  "// synthesis translate_on\n"
659  " end\n"
660  " 8'd115: //String\n"
661  " begin\n"
662  " _next_state=S_7;\n"
663  " _next_pointer1=0;\n"
664  " end\n"
665  " 8'd117: //unsigned int %u TO BE FIXED\n"
666  " if(data1_size ==8'd64)\n"
667  " begin\n"
668  "// synthesis translate_off\n"
669  " if(!write_done)\n"
670  " begin\n"
671  " $write(\"%0d\",$unsigned(data1));\n"
672  " write_done=1'b1;\n"
673  " end\n"
674  "// synthesis translate_on\n"
675  " end\n"
676  " else if(data1_size ==8'd32)\n"
677  " begin\n"
678  "// synthesis translate_off\n"
679  " if(!write_done)\n"
680  " begin\n"
681  " $write(\"%0d\",$unsigned(data1[31:0]));\n"
682  " write_done=1'b1;\n"
683  " end\n"
684  "// synthesis translate_on\n"
685  " end\n"
686  " else if(data1_size ==8'd16)\n"
687  " begin\n"
688  "// synthesis translate_off\n"
689  " if(!write_done)\n"
690  " begin\n"
691  " $write(\"%0d\",$unsigned(data1[15:0]));\n"
692  " write_done=1'b1;\n"
693  " end\n"
694  "// synthesis translate_on\n"
695  " end\n"
696  " else if(data1_size ==8'd8)\n"
697  " begin\n"
698  "// synthesis translate_off\n"
699  " if(!write_done)\n"
700  " begin\n"
701  " $write(\"%0d\",$unsigned(data1[7:0]));\n"
702  " write_done=1'b1;\n"
703  " end\n"
704  "// synthesis translate_on\n"
705  " end\n"
706  " else\n"
707  " begin\n"
708  "// synthesis translate_off\n"
709  " $display(\"ERROR - Unsigned precision not supported %d\", data1_size);\n"
710  " $finish;\n"
711  "// synthesis translate_on\n"
712  " end\n"
713  " 8'd120: //Hex %x\n"
714  " if(data1_size ==8'd64)\n"
715  " begin\n"
716  "// synthesis translate_off\n"
717  " if(!write_done)\n"
718  " begin\n"
719  " $write(\"%0h\",data1);\n"
720  " write_done=1'b1;\n"
721  " end\n"
722  "// synthesis translate_on\n"
723  " end\n"
724  " else if(data1_size ==8'd32)\n"
725  " begin\n"
726  "// synthesis translate_off\n"
727  " if(!write_done)\n"
728  " begin\n"
729  " $write(\"%0h\",data1[31:0]);\n"
730  " write_done=1'b1;\n"
731  " end\n"
732  "// synthesis translate_on\n"
733  " end\n"
734  " else if(data1_size ==8'd16)\n"
735  " begin\n"
736  "// synthesis translate_off\n"
737  " if(!write_done)\n"
738  " begin\n"
739  " $write(\"%0h\",data1[15:0]);\n"
740  " write_done=1'b1;\n"
741  " end\n"
742  "// synthesis translate_on\n"
743  " end\n"
744  " else if(data1_size ==8'd8)\n"
745  " begin\n"
746  "// synthesis translate_off\n"
747  " if(!write_done)\n"
748  " begin\n"
749  " $write(\"%0h\",data1[7:0]);\n"
750  " write_done=1'b1;\n"
751  " end\n"
752  "// synthesis translate_on\n"
753  " end\n"
754  " else\n"
755  " begin\n"
756  "// synthesis translate_off\n"
757  " $display(\"ERROR - Hex precision not supported %d\", data1_size);\n"
758  " $finish;\n"
759  "// synthesis translate_on\n"
760  " end\n"
761  " 8'd88: //Hex %X\n"
762  " if(data1_size ==8'd64)\n"
763  " begin\n"
764  "// synthesis translate_off\n"
765  " if(!write_done)\n"
766  " begin\n"
767  " $write(\"%0h\",data1);\n"
768  " write_done=1'b1;\n"
769  " end\n"
770  "// synthesis translate_on\n"
771  " end\n"
772  " else if(data1_size ==8'd32)\n"
773  " begin\n"
774  "// synthesis translate_off\n"
775  " if(!write_done)\n"
776  " begin\n"
777  " $write(\"%0h\",data1[31:0]);\n"
778  " write_done=1'b1;\n"
779  " end\n"
780  "// synthesis translate_on\n"
781  " end\n"
782  " else if(data1_size ==8'd16)\n"
783  " begin\n"
784  "// synthesis translate_off\n"
785  " if(!write_done)\n"
786  " begin\n"
787  " $write(\"%0h\",data1[15:0]);\n"
788  " write_done=1'b1;\n"
789  " end\n"
790  "// synthesis translate_on\n"
791  " end\n"
792  " else if(data1_size ==8'd8)\n"
793  " begin\n"
794  "// synthesis translate_off\n"
795  " if(!write_done)\n"
796  " begin\n"
797  " $write(\"%0h\",data1[7:0]);\n"
798  " write_done=1'b1;\n"
799  " end\n"
800  "// synthesis translate_on\n"
801  " end\n"
802  " else\n"
803  " begin\n"
804  "// synthesis translate_off\n"
805  " $display(\"ERROR - Hex precision not supported %d\", data1_size);\n"
806  " $finish;\n"
807  "// synthesis translate_on\n"
808  " end\n"
809  " default:\n"
810  " _next_state=S_3;\n"
811  " endcase\n"
812  " end\n"
813  " S_6:\n"
814  " begin\n"
815  " _next_selector=_present_selector<<1;\n"
816  " _next_state=S_1;\n"
817  " end\n"
818  " S_7:\n"
819  " begin\n"
820  " mem_in2 = data1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer1;\n"
821  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
822  " mem_sel_LOAD=1'b1;\n"
823  " if(mem_done_port)\n"
824  " begin\n"
825  " _next_data2 = mem_out1[7:0];\n"
826  " _next_state=S_4;\n"
827  "// synthesis translate_off\n"
828  " write_done=1'b0;\n"
829  "// synthesis translate_on\n"
830  " end\n"
831  " end\n"
832  " S_4:\n"
833  " begin\n"
834  " _next_pointer1=_present_pointer1+1'd1;\n"
835  " if(_present_data2!=8'd0)\n"
836  " begin\n"
837  "// synthesis translate_off\n"
838  " if(!write_done)\n"
839  " begin\n"
840  " $write(\"%c\",_present_data2);\n"
841  " write_done=1'b1;\n"
842  " end\n"
843  "// synthesis translate_on\n"
844  " _next_state=S_7;\n"
845  " end\n"
846  " else\n"
847  " _next_state=S_6;\n"
848  " end\n"
849  " endcase\n"
850  " end\n";
851 
852  out << fsm;
853 }
hls_manager.hpp
Data structure representing the entire HLS information.
PrintfP1NModuleGenerator::PrintfP1NModuleGenerator
PrintfP1NModuleGenerator(const HLS_managerRef &HLSMgr)
Definition: PrintfP1NModuleGenerator.cpp:54
STR
#define STR(s)
Macro which performs a lexical_cast to a string.
Definition: string_manipulation.hpp:52
HDLWriter_Language
HDLWriter_Language
Definition: language_writer.hpp:78
language_writer.hpp
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
vertex
boost::graph_traits< graph >::vertex_descriptor vertex
vertex definition.
Definition: graph.hpp:1303
bit_lattice::U
refcount
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
PrintfP1NModuleGenerator::InternalExec
void InternalExec(std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final
Definition: PrintfP1NModuleGenerator.cpp:58
memory.hpp
Datastructure to represent memory information in high-level synthesis.
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