PandA-2024.02
PrintfNModuleGenerator.cpp
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1 /*
2  *
3  * _/_/_/ _/_/ _/ _/ _/_/_/ _/_/
4  * _/ _/ _/ _/ _/_/ _/ _/ _/ _/ _/
5  * _/_/_/ _/_/_/_/ _/ _/_/ _/ _/ _/_/_/_/
6  * _/ _/ _/ _/ _/ _/ _/ _/ _/
7  * _/ _/ _/ _/ _/ _/_/_/ _/ _/
8  *
9  * ***********************************************
10  * PandA Project
11  * URL: http://panda.dei.polimi.it
12  * Politecnico di Milano - DEIB
13  * System Architectures Group
14  * ***********************************************
15  * Copyright (C) 2022-2024 Politecnico di Milano
16  *
17  * This file is part of the PandA framework.
18  *
19  * The PandA framework is free software; you can redistribute it and/or modify
20  * it under the terms of the GNU General Public License as published by
21  * the Free Software Foundation; either version 3 of the License, or
22  * (at your option) any later version.
23  *
24  * This program is distributed in the hope that it will be useful,
25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27  * GNU General Public License for more details.
28  *
29  * You should have received a copy of the GNU General Public License
30  * along with this program. If not, see <http://www.gnu.org/licenses/>.
31  *
32  */
47 #include "PrintfNModuleGenerator.hpp"
48 
49 #include "hls_manager.hpp"
50 #include "language_writer.hpp"
51 #include "memory.hpp"
52 
53 PrintfNModuleGenerator::PrintfNModuleGenerator(const HLS_managerRef& _HLSMgr) : Registrar(_HLSMgr)
54 {
55 }
56 
57 void PrintfNModuleGenerator::InternalExec(std::ostream& out, structural_objectRef /* mod */,
58  unsigned int /* function_id */, vertex /* op_v */,
59  const HDLWriter_Language /* language */,
60  const std::vector<ModuleGenerator::parameter>& _p,
61  const std::vector<ModuleGenerator::parameter>& /* _ports_in */,
62  const std::vector<ModuleGenerator::parameter>& /* _ports_out */,
63  const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
64 {
65  const auto selector_dimension = STR(_p.size() < 2U ? 2U : _p.size());
66  const auto selector_left = STR(((_p.size() - 1U) < 1U) ? 1U : (_p.size() - 1U));
67 
68  std::string sensitivity;
69  for(auto i = 0U; i < _p.size(); i++)
70  {
71  sensitivity += " or " + _p[i].name;
72  }
73 
74  std::string case_statement;
75  if(_p.size() > 1)
76  {
77  case_statement = "case (_present_selector)\n";
78  for(auto i = 0U, selector = 1U; i < _p.size(); i++, selector *= 2)
79  {
80  case_statement += " " + selector_dimension + "'d" + STR(selector) +
81  ":\n"
82  " begin\n"
83  " data1=" +
84  _p[i].name +
85  ";\n"
86  " data1_size=BITSIZE_in" +
87  STR(i + 1) +
88  ";\n"
89  " end\n";
90  }
91  case_statement += " default:\n"
92  " begin\n"
93  " data1 = 64'b0;\n"
94  " data1_size = 8'b0;\n"
95  " end\n"
96  " endcase";
97  }
98  else
99  {
100  case_statement = "";
101  }
102 
103  const auto fsm =
104  ""
105  "// synthesis translate_off\n"
106  "function real bits32_to_real64;\n"
107  " input [31:0] fin1;\n"
108  " reg [7:0] exponent1;\n"
109  " reg is_exp_zero;\n"
110  " reg is_all_ones;\n"
111  " reg [10:0] exp_tmp;\n"
112  " reg [63:0] fout1;\n"
113  "begin\n"
114  " exponent1 = fin1[30:23];\n"
115  " is_exp_zero = exponent1 == 8'd0;\n"
116  " is_all_ones = exponent1 == {8{1'b1}};\n"
117  " exp_tmp = {3'd0, exponent1} + 11'd896;\n"
118  " fout1[63] = fin1[31];\n"
119  " fout1[62:52] = is_exp_zero ? 11'd0 : (is_all_ones ? {11{1'b1}} : exp_tmp);\n"
120  " fout1[51:29] = fin1[22:0];\n"
121  " fout1[28:0] = 29'd0;\n"
122  " bits32_to_real64 = $bitstoreal(fout1);\n"
123  "end\n"
124  "endfunction\n"
125  "// synthesis translate_on\n"
126  "reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer;\n"
127  "reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer;\n"
128  "reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer1;\n"
129  "reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer1;\n"
130  "reg done_port;\n"
131  "reg [PORTSIZE_Mout_oe_ram-1:0] Mout_oe_ram;\n"
132  "reg [PORTSIZE_Mout_we_ram-1:0] Mout_we_ram;\n"
133  "reg [(PORTSIZE_Mout_addr_ram*BITSIZE_Mout_addr_ram)+(-1):0] Mout_addr_ram;\n"
134  "reg [(PORTSIZE_Mout_Wdata_ram*BITSIZE_Mout_Wdata_ram)+(-1):0] Mout_Wdata_ram;\n"
135  "reg [(PORTSIZE_Mout_data_ram_size*BITSIZE_Mout_data_ram_size)+(-1):0] Mout_data_ram_size;\n"
136  "reg active_request;\n"
137  "reg active_request_next;\n"
138  "\n"
139  "parameter [2:0] S_0 = 3'd0,\n"
140  " S_1 = 3'd1,\n"
141  " S_2 = 3'd2,\n"
142  " S_3 = 3'd3,\n"
143  " S_4 = 3'd4,\n"
144  " S_5 = 3'd5,\n"
145  " S_6 = 3'd6,\n"
146  " S_7 = 3'd7;\n"
147  "reg [2:0] _present_state;\n"
148  "reg [2:0] _next_state;\n"
149  "reg [" +
150  selector_left +
151  ":0] _present_selector;\n"
152  "reg [" +
153  selector_left +
154  ":0] _next_selector;\n"
155  "reg [63:0] data1;\n"
156  "reg [7:0] _present_data2;\n"
157  "reg [7:0] _next_data2;\n"
158  "reg [7:0] data1_size;\n"
159  "reg write_done;\n"
160  "\n"
161  " always @(posedge clock 1RESET_EDGE)\n"
162  " if (1RESET_VALUE)\n"
163  " begin\n"
164  " _present_state <= S_0;\n"
165  " _present_pointer <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
166  " _present_pointer1 <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
167  " _present_selector <=" +
168  selector_dimension +
169  "'d0;\n"
170  " _present_data2 <= 8'b0;\n"
171  " end\n"
172  " else\n"
173  " begin\n"
174  " _present_state <= _next_state;\n"
175  " _present_pointer <= _next_pointer;\n"
176  " _present_pointer1 <= _next_pointer1;\n"
177  " _present_selector <= _next_selector;\n"
178  " _present_data2 <= _next_data2;\n"
179  " end\n"
180  "\n"
181  " always @(posedge clock 1RESET_EDGE)\n"
182  " begin\n"
183  " if (1RESET_VALUE)\n"
184  " begin\n"
185  " active_request <= 0;\n"
186  " end\n"
187  " else\n"
188  " begin\n"
189  " active_request <= active_request_next;\n"
190  " end\n"
191  " end\n"
192  " always @(_present_state or _present_pointer or _present_pointer1 or _present_selector or start_port or "
193  "M_DataRdy[0] or Min_we_ram or Min_oe_ram or Min_Wdata_ram or Min_addr_ram or Min_data_ram_size" +
194  sensitivity +
195  " or _present_data2 or M_Rdata_ram[7:0])\n"
196  " begin\n"
197  " Mout_we_ram = Min_we_ram;\n"
198  " Mout_Wdata_ram = Min_Wdata_ram;\n"
199  " Mout_oe_ram=Min_oe_ram;\n"
200  " Mout_addr_ram=Min_addr_ram;\n"
201  " Mout_data_ram_size=Min_data_ram_size;\n"
202  " done_port = 1'b0;\n"
203  " active_request_next =1'b0;\n"
204  " _next_state = _present_state;\n"
205  " _next_pointer = _present_pointer;\n"
206  " _next_pointer1 = _present_pointer1;\n"
207  " _next_selector = _present_selector;\n"
208  " _next_data2 = _present_data2;\n"
209  " " +
210  case_statement +
211  "\n"
212  " case (_present_state)\n"
213  " S_0:\n"
214  " if(start_port)\n"
215  " begin\n"
216  " _next_pointer=0;\n"
217  " _next_pointer1=0;\n"
218  " _next_state=S_1; \n"
219  " active_request_next =1'b1;\n"
220  " _next_selector=" +
221  selector_dimension +
222  "'d2;\n"
223  " end\n"
224  " \n"
225  " S_1:\n"
226  " begin\n"
227  " Mout_addr_ram[BITSIZE_Mout_addr_ram-1:0]=(in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer) & "
228  "{BITSIZE_Mout_addr_ram{active_request}};\n"
229  " Mout_data_ram_size[BITSIZE_Mout_data_ram_size-1:0]={{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8} & "
230  "{BITSIZE_Mout_data_ram_size{active_request}};\n"
231  " Mout_oe_ram[0]=active_request;\n"
232  " if(M_DataRdy[0])\n"
233  " begin\n"
234  " _next_data2 = M_Rdata_ram[7:0];\n"
235  " _next_state=S_2;\n"
236  "// synthesis translate_off\n"
237  " write_done=1'b0;\n"
238  "// synthesis translate_on\n"
239  " end\n"
240  " end\n"
241  " S_2:\n"
242  " begin\n"
243  " _next_pointer=_present_pointer+1'd1;\n"
244  " if((_present_data2!=8'd0)&&(_present_data2!=8'd37))\n"
245  " begin\n"
246  "// synthesis translate_off\n"
247  " if(!write_done)\n"
248  " begin\n"
249  " $write(\"%c\",_present_data2);\n"
250  " write_done=1'b1;\n"
251  " end\n"
252  "// synthesis translate_on\n"
253  " _next_state=S_1;\n"
254  " active_request_next =1'b1;\n"
255  " end\n"
256  " else if(_present_data2==8'd37)\n"
257  " begin\n"
258  " _next_state=S_3;\n"
259  " active_request_next =1'b1;\n"
260  " end\n"
261  " else if(_present_data2==8'd0)\n"
262  " begin\n"
263  " done_port = 1'b1;\n"
264  " _next_state=S_0;\n"
265  " end\n"
266  " end\n"
267  " S_3:\n"
268  " begin\n"
269  " Mout_addr_ram[BITSIZE_Mout_addr_ram-1:0]=(in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer) & "
270  "{BITSIZE_Mout_addr_ram{active_request}};\n"
271  " Mout_data_ram_size[BITSIZE_Mout_data_ram_size-1:0]={{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8} & "
272  "{BITSIZE_Mout_data_ram_size{active_request}};\n"
273  " Mout_oe_ram[0]=active_request;\n"
274  " if(M_DataRdy[0])\n"
275  " begin\n"
276  " _next_data2 = M_Rdata_ram[7:0];\n"
277  " _next_state=S_5;\n"
278  "// synthesis translate_off\n"
279  " write_done=1'b0;\n"
280  "// synthesis translate_on\n"
281  " end\n"
282  " end\n"
283  " S_5 :\n"
284  " begin\n"
285  " _next_state=S_6;\n"
286  " _next_pointer=_present_pointer+1'd1;\n"
287  " case(_present_data2)\n"
288  " 8'd37: //%%\n"
289  " begin\n"
290  " _next_state=S_1;\n"
291  " active_request_next =1'b1;\n"
292  "// synthesis translate_off\n"
293  " if(!write_done)\n"
294  " begin\n"
295  " $write(\"%c\",8'd37);\n"
296  " write_done=1'b1;\n"
297  " end\n"
298  "// synthesis translate_on\n"
299  " end\n"
300  " 8'd99: //Char\n"
301  " begin\n"
302  "// synthesis translate_off\n"
303  " if(!write_done)\n"
304  " begin\n"
305  " $write(\"%c\",data1[7:0]);\n"
306  " write_done=1'b1;\n"
307  " end\n"
308  "// synthesis translate_on\n"
309  " end\n"
310  " 8'd100: //Decimal %d\n"
311  " if(data1_size ==8'd64)\n"
312  " begin\n"
313  "// synthesis translate_off\n"
314  " if(!write_done)\n"
315  " begin\n"
316  " $write(\"%0d\",$signed(data1));\n"
317  " write_done=1'b1;\n"
318  " end\n"
319  "// synthesis translate_on\n"
320  " end\n"
321  " else if(data1_size ==8'd32)\n"
322  " begin\n"
323  "// synthesis translate_off\n"
324  " if(!write_done)\n"
325  " begin\n"
326  " $write(\"%0d\",$signed(data1[31:0]));\n"
327  " write_done=1'b1;\n"
328  " end\n"
329  "// synthesis translate_on\n"
330  " end\n"
331  " else if(data1_size ==8'd16)\n"
332  " begin\n"
333  "// synthesis translate_off\n"
334  " if(!write_done)\n"
335  " begin\n"
336  " $write(\"%0d\",$signed(data1[15:0]));\n"
337  " write_done=1'b1;\n"
338  " end\n"
339  "// synthesis translate_on\n"
340  " end\n"
341  " else if(data1_size ==8'd8)\n"
342  " begin\n"
343  "// synthesis translate_off\n"
344  " if(!write_done)\n"
345  " begin\n"
346  " $write(\"%0d\",$signed(data1[7:0]));\n"
347  " write_done=1'b1;\n"
348  " end\n"
349  "// synthesis translate_on\n"
350  " end\n"
351  " else\n"
352  " begin\n"
353  "// synthesis translate_off\n"
354  " $display(\"ERROR - Decimal precision not supported (d) %d\", data1_size);\n"
355  " $finish;\n"
356  "// synthesis translate_on\n"
357  " end\n"
358  " 8'd105: //Decimal %i\n"
359  " if(data1_size ==8'd64)\n"
360  " begin\n"
361  "// synthesis translate_off\n"
362  " if(!write_done)\n"
363  " begin\n"
364  " $write(\"%0d\",$signed(data1));\n"
365  " write_done=1'b1;\n"
366  " end\n"
367  "// synthesis translate_on\n"
368  " end\n"
369  " else if(data1_size ==8'd32)\n"
370  " begin\n"
371  "// synthesis translate_off\n"
372  " if(!write_done)\n"
373  " begin\n"
374  " $write(\"%0d\",$signed(data1[31:0]));\n"
375  " write_done=1'b1;\n"
376  " end\n"
377  "// synthesis translate_on\n"
378  " end\n"
379  " else if(data1_size ==8'd16)\n"
380  " begin\n"
381  "// synthesis translate_off\n"
382  " if(!write_done)\n"
383  " begin\n"
384  " $write(\"%0d\",$signed(data1[15:0]));\n"
385  " write_done=1'b1;\n"
386  " end\n"
387  "// synthesis translate_on\n"
388  " end\n"
389  " else if(data1_size ==8'd8)\n"
390  " begin\n"
391  "// synthesis translate_off\n"
392  " if(!write_done)\n"
393  " begin\n"
394  " $write(\"%0d\",$signed(data1[7:0]));\n"
395  " write_done=1'b1;\n"
396  " end\n"
397  "// synthesis translate_on\n"
398  " end\n"
399  " else\n"
400  " begin\n"
401  "// synthesis translate_off\n"
402  " $display(\"ERROR - Decimal precision not supported (i) %d\", data1_size);\n"
403  " $finish;\n"
404  "// synthesis translate_on\n"
405  " end\n"
406  " 8'd101: //Exponential %e\n"
407  " begin\n"
408  " if(data1_size ==8'd64)\n"
409  " begin\n"
410  "// synthesis translate_off\n"
411  " if(!write_done)\n"
412  " begin\n"
413  " $write(\"%e\",$bitstoreal(data1));\n"
414  " write_done=1'b1;\n"
415  " end\n"
416  "// synthesis translate_on\n"
417  " end\n"
418  " else if(data1_size ==8'd32)\n"
419  " begin\n"
420  "// synthesis translate_off\n"
421  " if(!write_done)\n"
422  " begin\n"
423  " $write(\"%e\",bits32_to_real64(data1[31:0]));\n"
424  " write_done=1'b1;\n"
425  " end\n"
426  "// synthesis translate_on\n"
427  " end\n"
428  " else\n"
429  " begin\n"
430  "// synthesis translate_off\n"
431  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
432  " $finish;\n"
433  "// synthesis translate_on\n"
434  " end\n"
435  " end\n"
436  " 8'd69: //Exponential %E\n"
437  " begin\n"
438  " if(data1_size ==8'd64)\n"
439  " begin\n"
440  "// synthesis translate_off\n"
441  " if(!write_done)\n"
442  " begin\n"
443  " $write(\"%e\",$bitstoreal(data1));\n"
444  " write_done=1'b1;\n"
445  " end\n"
446  "// synthesis translate_on\n"
447  " end\n"
448  " else if(data1_size ==8'd32)\n"
449  " begin\n"
450  "// synthesis translate_off\n"
451  " if(!write_done)\n"
452  " begin\n"
453  " $write(\"%e\",bits32_to_real64(data1[31:0]));\n"
454  " write_done=1'b1;\n"
455  " end\n"
456  "// synthesis translate_on\n"
457  " end\n"
458  " else\n"
459  " begin\n"
460  "// synthesis translate_off\n"
461  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
462  " $finish;\n"
463  "// synthesis translate_on\n"
464  " end\n"
465  " end\n"
466  " 8'd102: //Float %f\n"
467  " begin\n"
468  " if(data1_size==8'd64)\n"
469  " begin\n"
470  "// synthesis translate_off\n"
471  " if(!write_done)\n"
472  " begin\n"
473  " $write(\"%20.20f\",$bitstoreal(data1));\n"
474  " write_done=1'b1;\n"
475  " end\n"
476  "// synthesis translate_on\n"
477  " end\n"
478  " else if(data1_size ==8'd32)\n"
479  " begin\n"
480  "// synthesis translate_off\n"
481  " if(!write_done)\n"
482  " begin\n"
483  " $write(\"%20.20f\",bits32_to_real64(data1[31:0]));\n"
484  " write_done=1'b1;\n"
485  " end\n"
486  "// synthesis translate_on\n"
487  " end\n"
488  " else\n"
489  " begin\n"
490  "// synthesis translate_off\n"
491  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
492  " $finish;\n"
493  "// synthesis translate_on\n"
494  " end\n"
495  " end\n"
496  " 8'd70: //Float %F\n"
497  " begin\n"
498  " if(data1_size==8'd64)\n"
499  " begin\n"
500  "// synthesis translate_off\n"
501  " if(!write_done)\n"
502  " begin\n"
503  " $write(\"%20.20f\",$bitstoreal(data1));\n"
504  " write_done=1'b1;\n"
505  " end\n"
506  "// synthesis translate_on\n"
507  " end\n"
508  " else if(data1_size ==8'd32)\n"
509  " begin\n"
510  "// synthesis translate_off\n"
511  " if(!write_done)\n"
512  " begin\n"
513  " $write(\"%20.20f\",bits32_to_real64(data1[31:0]));\n"
514  " write_done=1'b1;\n"
515  " end\n"
516  "// synthesis translate_on\n"
517  " end\n"
518  " else\n"
519  " begin\n"
520  "// synthesis translate_off\n"
521  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
522  " $finish;\n"
523  "// synthesis translate_on\n"
524  " end\n"
525  " end\n"
526  " 8'd103: //Float %g\n"
527  " begin\n"
528  " if(data1_size==8'd64)\n"
529  " begin\n"
530  "// synthesis translate_off\n"
531  " if(!write_done)\n"
532  " begin\n"
533  " $write(\"%20.20g\",$bitstoreal(data1));\n"
534  " write_done=1'b1;\n"
535  " end\n"
536  "// synthesis translate_on\n"
537  " end\n"
538  " else if(data1_size ==8'd32)\n"
539  " begin\n"
540  "// synthesis translate_off\n"
541  " if(!write_done)\n"
542  " begin\n"
543  " $write(\"%20.20g\",bits32_to_real64(data1[31:0]));\n"
544  " write_done=1'b1;\n"
545  " end\n"
546  "// synthesis translate_on\n"
547  " end\n"
548  " else\n"
549  " begin\n"
550  "// synthesis translate_off\n"
551  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
552  " $finish;\n"
553  "// synthesis translate_on\n"
554  " end\n"
555  " end\n"
556  " 8'd71: //Float %G\n"
557  " begin\n"
558  " if(data1_size==8'd64)\n"
559  " begin\n"
560  "// synthesis translate_off\n"
561  " if(!write_done)\n"
562  " begin\n"
563  " $write(\"%20.20g\",$bitstoreal(data1));\n"
564  " write_done=1'b1;\n"
565  " end\n"
566  "// synthesis translate_on\n"
567  " end\n"
568  " else if(data1_size ==8'd32)\n"
569  " begin\n"
570  "// synthesis translate_off\n"
571  " if(!write_done)\n"
572  " begin\n"
573  " $write(\"%20.20g\",bits32_to_real64(data1[31:0]));\n"
574  " write_done=1'b1;\n"
575  " end\n"
576  "// synthesis translate_on\n"
577  " end\n"
578  " else\n"
579  " begin\n"
580  "// synthesis translate_off\n"
581  " $display(\"ERROR - Floating point precision not supported %d\", data1_size);\n"
582  " $finish;\n"
583  "// synthesis translate_on\n"
584  " end\n"
585  " end\n"
586  " 8'd111: //Octal\n"
587  " if(data1_size ==8'd64)\n"
588  " begin\n"
589  "// synthesis translate_off\n"
590  " if(!write_done)\n"
591  " begin\n"
592  " $write(\"%0o\",data1);\n"
593  " write_done=1'b1;\n"
594  " end\n"
595  "// synthesis translate_on\n"
596  " end\n"
597  " else if(data1_size ==8'd32)\n"
598  " begin\n"
599  "// synthesis translate_off\n"
600  " if(!write_done)\n"
601  " begin\n"
602  " $write(\"%0o\",data1[31:0]);\n"
603  " write_done=1'b1;\n"
604  " end\n"
605  "// synthesis translate_on\n"
606  " end\n"
607  " else if(data1_size ==8'd16)\n"
608  " begin\n"
609  "// synthesis translate_off\n"
610  " if(!write_done)\n"
611  " begin\n"
612  " $write(\"%0o\",data1[15:0]);\n"
613  " write_done=1'b1;\n"
614  " end\n"
615  "// synthesis translate_on\n"
616  " end\n"
617  " else if(data1_size ==8'd8)\n"
618  " begin\n"
619  "// synthesis translate_off\n"
620  " if(!write_done)\n"
621  " begin\n"
622  " $write(\"%0o\",data1[7:0]);\n"
623  " write_done=1'b1;\n"
624  " end\n"
625  "// synthesis translate_on\n"
626  " end\n"
627  " else\n"
628  " begin\n"
629  "// synthesis translate_off\n"
630  " $display(\"ERROR - Octal precision not supported %d\", data1_size);\n"
631  " $finish;\n"
632  "// synthesis translate_on\n"
633  " end\n"
634  " 8'd112: //%p\n"
635  " begin\n"
636  "// synthesis translate_off\n"
637  " if(!write_done)\n"
638  " begin\n"
639  " $write(\"0x%0h\",data1);\n"
640  " write_done=1'b1;\n"
641  " end\n"
642  "// synthesis translate_on\n"
643  " end\n"
644  " 8'd115: //String\n"
645  " begin\n"
646  " _next_state=S_7;\n"
647  " active_request_next =1'b1;\n"
648  " _next_pointer1=0;\n"
649  " end\n"
650  " 8'd117: //unsigned int %u TO BE FIXED\n"
651  " if(data1_size ==8'd64)\n"
652  " begin\n"
653  "// synthesis translate_off\n"
654  " if(!write_done)\n"
655  " begin\n"
656  " $write(\"%0d\",$unsigned(data1));\n"
657  " write_done=1'b1;\n"
658  " end\n"
659  "// synthesis translate_on\n"
660  " end\n"
661  " else if(data1_size ==8'd32)\n"
662  " begin\n"
663  "// synthesis translate_off\n"
664  " if(!write_done)\n"
665  " begin\n"
666  " $write(\"%0d\",$unsigned(data1[31:0]));\n"
667  " write_done=1'b1;\n"
668  " end\n"
669  "// synthesis translate_on\n"
670  " end\n"
671  " else if(data1_size ==8'd16)\n"
672  " begin\n"
673  "// synthesis translate_off\n"
674  " if(!write_done)\n"
675  " begin\n"
676  " $write(\"%0d\",$unsigned(data1[15:0]));\n"
677  " write_done=1'b1;\n"
678  " end\n"
679  "// synthesis translate_on\n"
680  " end\n"
681  " else if(data1_size ==8'd8)\n"
682  " begin\n"
683  "// synthesis translate_off\n"
684  " if(!write_done)\n"
685  " begin\n"
686  " $write(\"%0d\",$unsigned(data1[7:0]));\n"
687  " write_done=1'b1;\n"
688  " end\n"
689  "// synthesis translate_on\n"
690  " end\n"
691  " else\n"
692  " begin\n"
693  "// synthesis translate_off\n"
694  " $display(\"ERROR - Unsigned precision not supported %d\", data1_size);\n"
695  " $finish;\n"
696  "// synthesis translate_on\n"
697  " end\n"
698  " 8'd120: //Hex %x\n"
699  " if(data1_size ==8'd64)\n"
700  " begin\n"
701  "// synthesis translate_off\n"
702  " if(!write_done)\n"
703  " begin\n"
704  " $write(\"%0h\",data1);\n"
705  " write_done=1'b1;\n"
706  " end\n"
707  "// synthesis translate_on\n"
708  " end\n"
709  " else if(data1_size ==8'd32)\n"
710  " begin\n"
711  "// synthesis translate_off\n"
712  " if(!write_done)\n"
713  " begin\n"
714  " $write(\"%0h\",data1[31:0]);\n"
715  " write_done=1'b1;\n"
716  " end\n"
717  "// synthesis translate_on\n"
718  " end\n"
719  " else if(data1_size ==8'd16)\n"
720  " begin\n"
721  "// synthesis translate_off\n"
722  " if(!write_done)\n"
723  " begin\n"
724  " $write(\"%0h\",data1[15:0]);\n"
725  " write_done=1'b1;\n"
726  " end\n"
727  "// synthesis translate_on\n"
728  " end\n"
729  " else if(data1_size ==8'd8)\n"
730  " begin\n"
731  "// synthesis translate_off\n"
732  " if(!write_done)\n"
733  " begin\n"
734  " $write(\"%0h\",data1[7:0]);\n"
735  " write_done=1'b1;\n"
736  " end\n"
737  "// synthesis translate_on\n"
738  " end\n"
739  " else\n"
740  " begin\n"
741  "// synthesis translate_off\n"
742  " $display(\"ERROR - Hex precision not supported %d\", data1_size);\n"
743  " $finish;\n"
744  "// synthesis translate_on\n"
745  " end\n"
746  " 8'd88: //Hex %X\n"
747  " if(data1_size ==8'd64)\n"
748  " begin\n"
749  "// synthesis translate_off\n"
750  " if(!write_done)\n"
751  " begin\n"
752  " $write(\"%0h\",data1);\n"
753  " write_done=1'b1;\n"
754  " end\n"
755  "// synthesis translate_on\n"
756  " end\n"
757  " else if(data1_size ==8'd32)\n"
758  " begin\n"
759  "// synthesis translate_off\n"
760  " if(!write_done)\n"
761  " begin\n"
762  " $write(\"%0h\",data1[31:0]);\n"
763  " write_done=1'b1;\n"
764  " end\n"
765  "// synthesis translate_on\n"
766  " end\n"
767  " else if(data1_size ==8'd16)\n"
768  " begin\n"
769  "// synthesis translate_off\n"
770  " if(!write_done)\n"
771  " begin\n"
772  " $write(\"%0h\",data1[15:0]);\n"
773  " write_done=1'b1;\n"
774  " end\n"
775  "// synthesis translate_on\n"
776  " end\n"
777  " else if(data1_size ==8'd8)\n"
778  " begin\n"
779  "// synthesis translate_off\n"
780  " if(!write_done)\n"
781  " begin\n"
782  " $write(\"%0h\",data1[7:0]);\n"
783  " write_done=1'b1;\n"
784  " end\n"
785  "// synthesis translate_on\n"
786  " end\n"
787  " else\n"
788  " begin\n"
789  "// synthesis translate_off\n"
790  " $display(\"ERROR - Hex precision not supported %d\", data1_size);\n"
791  " $finish;\n"
792  "// synthesis translate_on\n"
793  " end\n"
794  " default:\n"
795  " begin\n"
796  " _next_state=S_3;\n"
797  " active_request_next =1'b1;\n"
798  " end\n"
799  " endcase\n"
800  " end\n"
801  " S_6:\n"
802  " begin\n"
803  " _next_selector=_present_selector<<1;\n"
804  " _next_state=S_1;\n"
805  " active_request_next =1'b1;\n"
806  " end\n"
807  " S_7:\n"
808  " begin\n"
809  " Mout_addr_ram[BITSIZE_Mout_addr_ram-1:0]=(data1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer1) & "
810  "{BITSIZE_Mout_addr_ram{active_request}};\n"
811  " Mout_data_ram_size[BITSIZE_Mout_data_ram_size-1:0]={{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8} & "
812  "{BITSIZE_Mout_data_ram_size{active_request}};\n"
813  " Mout_oe_ram[0]=active_request;\n"
814  " if(M_DataRdy[0])\n"
815  " begin\n"
816  " _next_data2 = M_Rdata_ram[7:0];\n"
817  " _next_state=S_4;\n"
818  "// synthesis translate_off\n"
819  " write_done=1'b0;\n"
820  "// synthesis translate_on\n"
821  " end\n"
822  " end\n"
823  " S_4:\n"
824  " begin\n"
825  " _next_pointer1=_present_pointer1+1'd1;\n"
826  " if(_present_data2!=8'd0)\n"
827  " begin\n"
828  "// synthesis translate_off\n"
829  " if(!write_done)\n"
830  " begin\n"
831  " $write(\"%c\",_present_data2);\n"
832  " write_done=1'b1;\n"
833  " end\n"
834  "// synthesis translate_on\n"
835  " _next_state=S_7;\n"
836  " active_request_next =1'b1;\n"
837  " end\n"
838  " else\n"
839  " _next_state=S_6;\n"
840  " end\n"
841  " endcase\n"
842  " end\n";
843 
844  out << fsm;
845 }
hls_manager.hpp
Data structure representing the entire HLS information.
PrintfNModuleGenerator::InternalExec
void InternalExec(std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final
Definition: PrintfNModuleGenerator.cpp:57
STR
#define STR(s)
Macro which performs a lexical_cast to a string.
Definition: string_manipulation.hpp:52
HDLWriter_Language
HDLWriter_Language
Definition: language_writer.hpp:78
language_writer.hpp
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
vertex
boost::graph_traits< graph >::vertex_descriptor vertex
vertex definition.
Definition: graph.hpp:1303
bit_lattice::U
PrintfNModuleGenerator::PrintfNModuleGenerator
PrintfNModuleGenerator(const HLS_managerRef &HLSMgr)
Definition: PrintfNModuleGenerator.cpp:53
refcount
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
memory.hpp
Datastructure to represent memory information in high-level synthesis.
Generated on Mon Feb 12 2024 13:02:54 for PandA-2024.02 by doxygen 1.8.13