PandA-2024.02
OpenCSModuleGenerator.cpp
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46 #include "OpenCSModuleGenerator.hpp"
47 
48 #include "hls_manager.hpp"
49 #include "language_writer.hpp"
50 #include "memory.hpp"
51 #include <fcntl.h>
52 
53 OpenCSModuleGenerator::OpenCSModuleGenerator(const HLS_managerRef& _HLSMgr) : Registrar(_HLSMgr)
54 {
55 }
56 
57 void OpenCSModuleGenerator::InternalExec(std::ostream& out, structural_objectRef /* mod */,
58  unsigned int /* function_id */, vertex /* op_v */,
59  const HDLWriter_Language /* language */,
60  const std::vector<ModuleGenerator::parameter>& _p,
61  const std::vector<ModuleGenerator::parameter>& /* _ports_in */,
62  const std::vector<ModuleGenerator::parameter>& /* _ports_out */,
63  const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
64 {
65  const auto data_bus_bitsize = STR(HLSMgr->Rmem->get_bus_data_bitsize());
66  const auto addr_bus_bitsize = STR(HLSMgr->get_address_bitsize());
67  const auto size_bus_bitsize = STR(HLSMgr->Rmem->get_bus_size_bitsize());
68 
69  out << " // verilator lint_off LITENDIAN\n";
70  out << "parameter MAX_BUFF_SIZE = 256;\n";
71  out << "reg [0:8*MAX_BUFF_SIZE-1] buffer_name;\n";
72  out << "\n";
73  out << " `ifndef _SIM_HAVE_CLOG2\n";
74  out << " function integer log2;\n";
75  out << " input integer value;\n";
76  out << " integer temp_value;\n";
77  out << " begin\n";
78  out << " temp_value = value-1;\n";
79  out << " for (log2=0; temp_value>0; log2=log2+1)\n";
80  out << " temp_value = temp_value>>1;\n";
81  out << " end\n";
82  out << " endfunction\n";
83  out << " `endif\n";
84  out << "\n";
85  out << " `ifdef _SIM_HAVE_CLOG2\n";
86  out << " parameter nbits_buffer = $clog2(MAX_BUFF_SIZE);\n";
87  out << " `else\n";
88  out << " parameter nbits_buffer = log2(MAX_BUFF_SIZE);\n";
89  out << " `endif\n";
90 
91  std::string sensitivity;
92  for(auto i = 0U; i < _p.size(); i++)
93  {
94  sensitivity += " or " + _p[i].name;
95  }
96 
97  std::string modes = "in2";
98 
99  std::string flags_string = "(" + modes + " & " + STR(O_RDWR) + ") != 0 && (" + modes + " & " + STR(O_APPEND) +
100  ") ? \"a+b\" : ((" + modes + " & " + STR(O_RDWR) + ") != 0 ? \"r+b\" : ((" + modes +
101  " & " + STR(O_WRONLY) + ") != 0 && (" + modes + " & " + STR(O_APPEND) + ") ? \"ab\" : (" +
102  modes + " & " + STR(O_WRONLY) + ") != 0 ? \"wb\" : \"rb\"" + "))";
103 
104  const auto fsm =
105  " reg [nbits_buffer-1:0] _present_index;\n"
106  " reg [nbits_buffer-1:0] _next_index;\n"
107  " reg [BITSIZE_Mout_addr_ram-1:0] _present_pointer;\n"
108  " reg [BITSIZE_Mout_addr_ram-1:0] _next_pointer;\n"
109  " reg done_port;\n"
110  " wire mem_done_port;\n"
111  " reg signed [BITSIZE_out1-1:0] temp_out1;\n"
112  " \n"
113  " parameter [2:0] S_0 = 3'd0,\n"
114  " S_1 = 3'd1,\n"
115  " S_2 = 3'd2,\n"
116  " S_3 = 3'd3,\n"
117  " S_4 = 3'd4;\n"
118  " reg [2:0] _present_state;\n"
119  " reg [2:0] _next_state;\n"
120  " reg [63:0] data1;\n"
121  " reg [7:0] data1_size;\n"
122  " wire [" +
123  data_bus_bitsize +
124  "-1:0] mem_out1;\n"
125  " reg [" +
126  addr_bus_bitsize +
127  "-1:0] mem_in2;\n"
128  " reg [" +
129  size_bus_bitsize +
130  "-1:0] mem_in3;\n"
131  " reg mem_sel_LOAD;\n"
132  " reg start_memory_op;\n"
133  " mem_ctrl_kernel #(.TAG_MEM_REQ(0), .BITSIZE_in1(" +
134  data_bus_bitsize + "), .BITSIZE_in2(" + addr_bus_bitsize + "), .BITSIZE_in3(" + size_bus_bitsize +
135  "), .BITSIZE_out1(" + data_bus_bitsize +
136  "), .BITSIZE_Mout_oe_ram(BITSIZE_Mout_oe_ram), .BITSIZE_Mout_we_ram(BITSIZE_Mout_we_ram), "
137  ".BITSIZE_Mout_addr_ram(BITSIZE_Mout_addr_ram), .BITSIZE_Mout_data_ram_size(BITSIZE_Mout_data_ram_size), "
138  ".BITSIZE_Mout_Wdata_ram(BITSIZE_Mout_Wdata_ram), .BITSIZE_Mout_tag_ram(BITSIZE_Mout_tag_ram), "
139  ".BITSIZE_M_Rdata_ram(BITSIZE_M_Rdata_ram), .BITSIZE_M_DataRdy(BITSIZE_M_DataRdy), "
140  ".BITSIZE_Min_tag(BITSIZE_Min_tag), .BITSIZE_request_accepted(BITSIZE_request_accepted)) "
141  "mem_ctrl_kernel_instance (.clock(clock), .in1(0), .in2(mem_in2), .in3(mem_in3), .sel_LOAD(mem_sel_LOAD), "
142  ".sel_STORE(1'b0), .done_port(mem_done_port), .out1(mem_out1), .Mout_oe_ram(Mout_oe_ram), "
143  ".Mout_we_ram(Mout_we_ram), .Mout_addr_ram(Mout_addr_ram), .Mout_data_ram_size(Mout_data_ram_size), "
144  ".Mout_Wdata_ram(Mout_Wdata_ram), .Mout_tag_ram(Mout_tag_ram), .M_Rdata_ram(M_Rdata_ram), "
145  ".M_DataRdy(M_DataRdy), .Min_tag(Min_tag), .request_accepted(request_accepted), .start_port(start_memory_op));\n"
146  " \n"
147  " \n"
148  " always @(posedge clock 1RESET_EDGE)\n"
149  " if (1RESET_VALUE)\n"
150  " begin\n"
151  " _present_state <= S_0;\n"
152  " _present_pointer <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
153  " _present_index <= {nbits_buffer{1'b0}};\n"
154  " end\n"
155  " else\n"
156  " begin\n"
157  " _present_state <= _next_state;\n"
158  " _present_pointer <= _next_pointer;\n"
159  " _present_index <= _next_index;\n"
160  " end\n"
161  " \n"
162  " assign out1 = {1'b0,temp_out1[30:0]};"
163  " always @(_present_state or _present_pointer or _present_index or start_port or mem_done_port" +
164  sensitivity +
165  " or mem_out1 or M_DataRdy)\n"
166  " begin\n"
167  " done_port = 1'b0;\n"
168  " _next_state = _present_state;\n"
169  " _next_pointer = _present_pointer;\n"
170  " _next_index = _present_index;\n"
171  " mem_sel_LOAD = 1'b0;\n"
172  " start_memory_op= 1'b0;\n"
173  " mem_in2=" +
174  addr_bus_bitsize +
175  "'d0;\n"
176  " mem_in3=" +
177  size_bus_bitsize +
178  "'d0;\n"
179  " case (_present_state)\n"
180  " S_0:\n"
181  " if(start_port)\n"
182  " begin\n"
183  " _next_pointer=0;\n"
184  " _next_index={nbits_buffer{1'b0}};\n"
185  " _next_state=S_1; \n"
186  " buffer_name=0; \n"
187  " end\n"
188  " \n"
189  " S_1:\n"
190  " begin\n"
191  " mem_in2 = in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer;\n"
192  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
193  " mem_sel_LOAD=1'b1;\n"
194  " start_memory_op= 1'b1;\n"
195  " if(mem_done_port)\n"
196  " begin\n"
197  " buffer_name[_present_index*8 +:8] = mem_out1[7:0];\n"
198  " if(mem_out1[7:0] == 8'd0)\n"
199  " _next_state=S_2;\n"
200  " else\n"
201  " _next_state=S_3;\n"
202  " end\n"
203  " else begin\n"
204  " _next_state=S_4;\n"
205  " end\n"
206  " end\n"
207  " S_4:\n"
208  " begin\n"
209  " mem_in2 = in1[BITSIZE_Mout_addr_ram-1:0]+_present_pointer;\n"
210  " mem_in3 = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8};\n"
211  " mem_sel_LOAD=1'b1;\n"
212  " if(mem_done_port)\n"
213  " begin\n"
214  " buffer_name[_present_index*8 +:8] = mem_out1[7:0];\n"
215  " if(mem_out1[7:0] == 8'd0)\n"
216  " _next_state=S_2;\n"
217  " else\n"
218  " _next_state=S_3;\n"
219  " end\n"
220  " end\n"
221  " S_2:\n"
222  " begin\n"
223  "// synthesis translate_off\n"
224  " temp_out1 = $fopen(buffer_name, " +
225  flags_string +
226  ");\n"
227  "// synthesis translate_on\n"
228  " done_port = 1'b1;\n"
229  " _next_state=S_0;\n"
230  " end\n"
231  " S_3:\n"
232  " begin\n"
233  " if(!mem_done_port)\n"
234  " begin\n"
235  " _next_pointer=_present_pointer+1'd1;\n"
236  " _next_index=_present_index+1'd1;\n"
237  " _next_state=S_1;\n"
238  " end\n"
239  " end\n"
240  " endcase\n"
241  " end\n";
242 
243  out << fsm;
244  out << " // verilator lint_on LITENDIAN\n";
245 }
hls_manager.hpp
Data structure representing the entire HLS information.
STR
#define STR(s)
Macro which performs a lexical_cast to a string.
Definition: string_manipulation.hpp:52
HDLWriter_Language
HDLWriter_Language
Definition: language_writer.hpp:78
OpenCSModuleGenerator::InternalExec
void InternalExec(std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final
Definition: OpenCSModuleGenerator.cpp:57
language_writer.hpp
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
vertex
boost::graph_traits< graph >::vertex_descriptor vertex
vertex definition.
Definition: graph.hpp:1303
bit_lattice::U
OpenCSModuleGenerator::OpenCSModuleGenerator
OpenCSModuleGenerator(const HLS_managerRef &HLSMgr)
Definition: OpenCSModuleGenerator.cpp:53
refcount
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
memory.hpp
Datastructure to represent memory information in high-level synthesis.
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