42 #ifndef RTL_CHARACTERIZATION_HPP 43 #define RTL_CHARACTERIZATION_HPP 108 unsigned int bus_addr_bitsize,
unsigned int bus_size_bitsize,
unsigned int bus_tag_bitsize,
109 size_t portsize_value);
147 const std::string& register_library);
172 const size_t portsize_index,
const std::vector<std::string>& pipe_parameters,
173 const size_t stage_index,
const unsigned int constPort,
const bool is_commutative,
174 size_t max_lut_size)
override;
213 std::string
GetName()
const override;
generic device description
void ComputeRelationships(DesignFlowStepSet &relationship, const DesignFlowStep::RelationshipType relationship_type) override
Compute the relationships of a step with other steps.
void resize_port(const structural_objectRef &port, unsigned int prec)
resize the port w.r.t a given precision
void xwrite_characterization(xml_element *nodeRoot)
Add the characterization to the output file.
REF_FORWARD_DECL(area_info)
void add_output_register(structural_managerRef SM, structural_objectRef e_port, structural_objectRef circuit, structural_objectRef reset_port, structural_objectRef port_out, const std::string &port_prefix, structural_objectRef clock_port, const std::string ®ister_library)
CONSTREF_FORWARD_DECL(Parameter)
DesignFlowStep_Status Exec() override
Perform RTL characterization of the modules with respect to the target device.
RelationshipType
The relationship type.
DesignFlowStepFactoryConstRef CGetDesignFlowStepFactory() const override
Return the factory to create this type of steps.
area_infoRef prev_area_characterization
The area model of the last characterization.
void add_input_register(structural_objectRef port_in, const std::string ®ister_library, const std::string &port_prefix, structural_objectRef reset_port, structural_objectRef circuit, structural_objectRef clock_port, structural_objectRef e_port, structural_managerRef SM)
This class manages the circuit structures.
This class specifies the characteristic of a particular functional unit.
const CustomSet< std::string > cells
The cells to be characterized.
Abstract class to iterate over all the cells of a template.
time_infoRef prev_timing_characterization
The time model of the last characterization.
const CustomSet< std::string > ComputeCells(const std::string &input) const
Extract the cell lists.
void characterize_fu(const technology_nodeRef functional_unit)
Characterize the given functional unit with respect to the target device.
void fix_proxies_execution_time_std()
Fix execution/stage period value for proxies and bounded memory controllers.
CustomOrderedSet< std::string > completed
set of units completed with success
This class manages the technology library structures.
RTLCharacterization(const generic_deviceRef _device, const std::string &_cells, const DesignFlowManagerConstRef design_flow_manager, const ParameterConstRef parameters)
Constructor.
redefinition of set to manage ordered/unordered structures
const std::string component
The component to be characterized.
const Wrefcount< const DesignFlowManager > design_flow_manager
The design flow manager.
const ParameterConstRef parameters
Set of input parameters.
DesignFlowStep_Status
The status of a step.
bool HasToBeExecuted() const override
Check if this step has actually to be executed.
void fix_execution_time_std()
Fix the execution time by removing set/hold/pad timings.
Template definition of refcount.
void fix_muxes()
fix the estimation of mux timing
This class manages the specific library structure.
library_managerRef LM
Library manager.
~RTLCharacterization() override
Destructor.
std::string GetName() const override
Return the name of this design step.
HDL writer base class used to specify the interface of the different language writers.
const bool dummy_synthesis
True if we are performing dummy synthesis.
std::string GetSignature() const override
Return a unified identifier of this design step.
void specialize_fu(const module *mod, unsigned int prec, unsigned int bus_data_bitsize, unsigned int bus_addr_bitsize, unsigned int bus_size_bitsize, unsigned int bus_tag_bitsize, size_t portsize_value)
Performing the specialization of the given object.
void AnalyzeCell(functional_unit *fu, const unsigned int prec, const std::vector< std::string > &portsize_parameters, const size_t portsize_index, const std::vector< std::string > &pipe_parameters, const size_t stage_index, const unsigned int constPort, const bool is_commutative, size_t max_lut_size) override
Analyze the single cell.
void xwrite_device_file()
Generate the output file.
void Initialize() override
Initialize the step (i.e., like a constructor, but executed just before exec.
This class describes a generic module.
Abstract pure class for the technology structure.
const std::string ComputeComponent(const std::string &input) const
Extract the component name from list of cells.
Base object for all the structural objects.
Step which loads device dependent technology information.