HDL writer base class used to specify the interface of the different language writers. More...

#include <language_writer.hpp>

Inheritance diagram for language_writer:

Collaboration diagram for language_writer:

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Public Member Functions
	language_writer (char open_char, char close_char, const ParameterConstRef parameters)
	Constructor. More...

virtual	~language_writer ()
	Destructor. More...

virtual std::string	get_name () const =0
	Returns the name of the language writer. More...

virtual std::string	get_extension () const =0
	Returns the filename extension associated with the specification. More...

virtual void	write (const std::string &rawString)
	Writes a raw string into the stream. More...

virtual void	write_header ()
	Writes the header part of the file. More...

virtual void	write_comment (const std::string &comment_string)=0
	Prints a comment. More...

virtual std::string	type_converter (structural_type_descriptorRef Type)=0
	Return a language based type string given a structural_type_descriptor. More...

virtual std::string	type_converter_size (const structural_objectRef &cir)=0
	Return a language based size string given the object. More...

virtual void	write_library_declaration (const structural_objectRef &cir)=0
	Write the declaration of the library. More...

virtual void	write_module_declaration (const structural_objectRef &cir)=0
	Write the declaration of the module. More...

virtual void	write_module_internal_declaration (const structural_objectRef &cir)=0
	Write the declaration of internal objects of the module. More...

virtual void	write_port_declaration (const structural_objectRef &cir, bool first_port_analyzed)=0
	Write the port declaration starting from a port object. More...

virtual void	write_component_declaration (const structural_objectRef &cir)=0
	Write the declaration of componets. More...

virtual void	write_signal_declaration (const structural_objectRef &cir)=0
	Write the declaration of a signal. More...

virtual void	write_module_definition_begin (const structural_objectRef &cir)=0
	Write the begin part in a module declaration. More...

virtual void	write_module_instance_begin (const structural_objectRef &cir, const std::string &module_name, bool write_parametrization)=0
	Write the initial part of the instance of a module. More...

virtual void	write_module_instance_end (const structural_objectRef &cir)=0
	Write the ending part of the instance of a module. More...

virtual void	write_port_binding (const structural_objectRef &port, const structural_objectRef &top, bool first_port_analyzed)=0
	Write the binding of a port. More...

virtual void	write_vector_port_binding (const structural_objectRef &port, bool first_port_analyzed)=0

virtual void	write_module_definition_end (const structural_objectRef &cir)=0
	Write the end part in a module declaration. More...

virtual void	write_io_signal_post_fix (const structural_objectRef &port, const structural_objectRef &sig)=0
	Write some code managing primary ports to signals connections. More...

virtual void	write_io_signal_post_fix_vector (const structural_objectRef &port, const structural_objectRef &sig)=0

virtual void	write_module_parametrization (const structural_objectRef &cir)=0
	Module can be parametrized with respect different features. More...

virtual void	write_state_declaration (const structural_objectRef &cir, const std::list< std::string > &list_of_states, const std::string &reset_port, const std::string &reset_state, bool one_hot)=0
	write the declaration of all the states of the finite state machine. More...

virtual void	write_present_state_update (const structural_objectRef cir, const std::string &reset_state, const std::string &reset_port, const std::string &clock_port, const std::string &reset_type, bool connect_present_next_state_signals)=0
	write the present_state update process More...

virtual void	write_transition_output_functions (bool single_proc, unsigned int output_index, const structural_objectRef &cir, const std::string &reset_state, const std::string &reset_port, const std::string &start_port, const std::string &clock_port, std::vector< std::string >::const_iterator &first, std::vector< std::string >::const_iterator &end, bool is_yosys, const std::map< unsigned int, std::map< std::string, std::set< unsigned int >>> &bypass_signals)=0
	Write the transition and output functions. More...

virtual void	write_NP_functionalities (const structural_objectRef &cir)=0
	Write in the proper language the behavioral description of the module described in "Not Parsed" form. More...

virtual void	write_port_decl_header ()=0
	Write the header for generics. More...

virtual void	write_port_decl_tail ()=0
	Write the tail for generics. More...

virtual void	write_module_parametrization_decl (const structural_objectRef &cir)=0
	Write the declaration of the module parameters. More...

virtual void	write_assign (const std::string &op0, const std::string &op1)=0

virtual bool	has_output_prefix () const =0

virtual bool	check_keyword (const std::string &id) const =0

virtual void	WriteBuiltin (const structural_objectConstRef component)=0
	Write a builtin component. More...

const std::string	WriteString () const
	Dump the content of the write as a string. More...

void	WriteFile (const std::string &filename) const
	Write content to a file. More...

CustomSet< std::string >	GetHDLReservedNames () const
	Return the names of auxiliary signals which will be used by backend. More...

void	WriteLicense ()
	Write the license. More...

Static Public Member Functions
static language_writerRef	create_writer (HDLWriter_Language language, const technology_managerConstRef TM, const ParameterConstRef parameters)
	Creates the specialization of the writer based on the desired language. More...

static unsigned int	bitnumber (unsigned long long n)
	Counts the number of bits in an unsigned int. More...

Protected Member Functions
std::string	encode_one_hot (unsigned int n_states, unsigned int val) const

Protected Attributes
const IndentedOutputStreamRef	indented_output_stream
	Represents the stream we are currently writing to. More...

CustomOrderedSet< std::string >	list_of_lib
	list of library imported (e.g., includes). More...

CustomOrderedSet< std::string >	list_of_customized_gates
	list of customized gates More...

const ParameterConstRef	parameters
	the set of input parameters More...

int	debug_level
	debugging level of the class More...

Detailed Description

HDL writer base class used to specify the interface of the different language writers.

Definition at line 88 of file language_writer.hpp.

Constructor & Destructor Documentation

◆ language_writer()

language_writer::language_writer	(	char	open_char,
		char	close_char,
		const ParameterConstRef	_parameters
	)

Constructor.

constants include

. include utility include

Definition at line 63 of file language_writer.cpp.

References ~language_writer().

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◆ ~language_writer()

language_writer::~language_writer ( )

virtualdefault

Destructor.

Referenced by language_writer().

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Member Function Documentation

◆ bitnumber()

unsigned int language_writer::bitnumber ( unsigned long long n )

static

Counts the number of bits in an unsigned int.

Parameters

n	is the number.

Definition at line 72 of file language_writer.cpp.

Referenced by comp_state_bitsize(), HWDiscrepancyAnalysis::Exec(), VHDL_writer::write_state_declaration(), and verilog_writer::write_state_declaration().

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◆ check_keyword()

virtual bool language_writer::check_keyword ( const std::string & id ) const

pure virtual

Implemented in verilog_writer, and VHDL_writer.

Referenced by HDL_manager::convert_to_identifier().

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◆ create_writer()

language_writerRef language_writer::create_writer	(	HDLWriter_Language	language,
		const technology_managerConstRef	TM,
		const ParameterConstRef	parameters
	)

static

Creates the specialization of the writer based on the desired language.

Parameters

language_w	is the desired language
TM	is the technology manager
parameters	is the set of input parameters

Definition at line 87 of file language_writer.cpp.

References SYSTEM_VERILOG, THROW_ASSERT, THROW_ERROR, VERILOG, and VHDL.

Referenced by allocation::BuildProxyFunctionVerilog(), allocation::BuildProxyFunctionVHDL(), GenerateTasteHDLArchitecture::Exec(), HDLFunctionDeclFix::Exec(), TestbenchGeneration::Exec(), HDLVarDeclFix::InternalExec(), HDL_manager::write_components(), and HDL_manager::write_flopoco_module().

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◆ encode_one_hot()

std::string language_writer::encode_one_hot	(	unsigned int	n_states,
		unsigned int	val
	)		const

inlineprotected

Definition at line 91 of file language_writer.hpp.

Referenced by VHDL_writer::write_state_declaration(), and verilog_writer::write_state_declaration().

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◆ get_extension()

virtual std::string language_writer::get_extension ( ) const

pure virtual

Returns the filename extension associated with the specification.

Implemented in VHDL_writer, verilog_writer, and system_verilog_writer.

◆ get_name()

virtual std::string language_writer::get_name ( ) const

pure virtual

Returns the name of the language writer.

Implemented in VHDL_writer, verilog_writer, and system_verilog_writer.

◆ GetHDLReservedNames()

CustomSet< std::string > language_writer::GetHDLReservedNames ( ) const

Return the names of auxiliary signals which will be used by backend.

Definition at line 128 of file language_writer.cpp.

References CLOCK_PORT_NAME, COPYING3_SHORT_MACRO, DONE_PORT_NAME, RESET_PORT_NAME, RETURN_PORT_NAME, START_PORT_NAME, and WENABLE_PORT_NAME.

◆ has_output_prefix()

virtual bool language_writer::has_output_prefix ( ) const

pure virtual

Implemented in verilog_writer, and VHDL_writer.

◆ type_converter()

virtual std::string language_writer::type_converter ( structural_type_descriptorRef Type )

pure virtual

Return a language based type string given a structural_type_descriptor.

Parameters

Type	is the structural_type_descriptor.

Implemented in verilog_writer, and VHDL_writer.

◆ type_converter_size()

virtual std::string language_writer::type_converter_size ( const structural_objectRef & cir )

pure virtual

Return a language based size string given the object.

Parameters

cir	is the object

Implemented in verilog_writer, and VHDL_writer.

◆ write()

void language_writer::write ( const std::string & rawString )

virtual

Writes a raw string into the stream.

Parameters

rawString is the string to be written.

Definition at line 109 of file language_writer.cpp.

References IndentedOutputStream::Append(), and indented_output_stream.

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◆ write_assign()

virtual void language_writer::write_assign	(	const std::string &	op0,
		const std::string &	op1
	)

pure virtual

Implemented in verilog_writer, and VHDL_writer.

◆ write_comment()

virtual void language_writer::write_comment ( const std::string & comment_string )

pure virtual

Prints a comment.

Parameters

comment_string is the string to be printed as a comment.

Implemented in VHDL_writer, and verilog_writer.

Referenced by WriteLicense().

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◆ write_component_declaration()

virtual void language_writer::write_component_declaration ( const structural_objectRef & cir )

pure virtual

Write the declaration of componets.

Parameters

cir	is the component to be declared.

Implemented in verilog_writer, and VHDL_writer.

◆ write_header()

void language_writer::write_header ( )

virtual

Writes the header part of the file.

Write some lines of comments and possibly global libraries.

Reimplemented in VHDL_writer, and verilog_writer.

Definition at line 114 of file language_writer.cpp.

◆ write_io_signal_post_fix()

virtual void language_writer::write_io_signal_post_fix	(	const structural_objectRef &	port,
		const structural_objectRef &	sig
	)

pure virtual

Write some code managing primary ports to signals connections.

Loop signals are present for example in this bench circuit: INPUT(X) OUTPUT(Z) Y = DFF(Z) Z = AND(X,Y) The circuit builder adds an internal signal Z_sign allowing the write and read of the Z values.

Parameters

port	is the primary port for which this problem happens.
sig	is the attached signal.

Implemented in verilog_writer, and VHDL_writer.

◆ write_io_signal_post_fix_vector()

virtual void language_writer::write_io_signal_post_fix_vector	(	const structural_objectRef &	port,
		const structural_objectRef &	sig
	)

pure virtual

Implemented in verilog_writer, and VHDL_writer.

◆ write_library_declaration()

virtual void language_writer::write_library_declaration ( const structural_objectRef & cir )

pure virtual

Write the declaration of the library.

Parameters

cir	is the component for which the library declarations are written.

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_declaration()

virtual void language_writer::write_module_declaration ( const structural_objectRef & cir )

pure virtual

Write the declaration of the module.

Parameters

cir	is the module to be written.

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_definition_begin()

virtual void language_writer::write_module_definition_begin ( const structural_objectRef & cir )

pure virtual

Write the begin part in a module declaration.

Parameters

cir	is the top component to be declared.

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_definition_end()

virtual void language_writer::write_module_definition_end ( const structural_objectRef & cir )

pure virtual

Write the end part in a module declaration.

Parameters

cir	is the top component to be declared.

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_instance_begin()

virtual void language_writer::write_module_instance_begin	(	const structural_objectRef &	cir,
		const std::string &	module_name,
		bool	write_parametrization
	)

pure virtual

Write the initial part of the instance of a module.

Parameters

cir	is the module to be instanced.
component_name	is the name of the module to be instanced. It has to be specified since VHDL and verilog can print in different ways

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_instance_end()

virtual void language_writer::write_module_instance_end ( const structural_objectRef & cir )

pure virtual

Write the ending part of the instance of a module.

Parameters

cir	is the module to be instanced.

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_internal_declaration()

virtual void language_writer::write_module_internal_declaration ( const structural_objectRef & cir )

pure virtual

Write the declaration of internal objects of the module.

Parameters

cir	is the module to be written.

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_parametrization()

virtual void language_writer::write_module_parametrization ( const structural_objectRef & cir )

pure virtual

Module can be parametrized with respect different features.

Port vectors are parametrized with the number of port associated, while ports are parametrized in case the type is a integer with the number of bits. The id of the module is modified by adding the parameters at its end. For example an AND_GATE with a port_vector of 2 will be declared as: AND_GATE_2. Moreover, a multiplier with the first input of four bits, the second input with eight bits and an output of twelve bits will be declared as: MULT_4_8_12. Note that parametrization has a meaning only in case the functionality come from the STD technology library.

Parameters

cir	is the component to be declared.

Implemented in verilog_writer, and VHDL_writer.

◆ write_module_parametrization_decl()

virtual void language_writer::write_module_parametrization_decl ( const structural_objectRef & cir )

pure virtual

Write the declaration of the module parameters.

Implemented in verilog_writer, and VHDL_writer.

◆ write_NP_functionalities()

virtual void language_writer::write_NP_functionalities ( const structural_objectRef & cir )

pure virtual

Write in the proper language the behavioral description of the module described in "Not Parsed" form.

Parameters

cir	is the component.

Implemented in verilog_writer, VHDL_writer, and system_verilog_writer.

◆ write_port_binding()

virtual void language_writer::write_port_binding	(	const structural_objectRef &	port,
		const structural_objectRef &	top,
		bool	first_port_analyzed
	)

pure virtual

Write the binding of a port.

It follows the name binding style.

Parameters

port	is the port to be bounded.
top	is the component owner of the component that has the port to be bounded.

Implemented in verilog_writer, and VHDL_writer.

◆ write_port_decl_header()

virtual void language_writer::write_port_decl_header ( )

pure virtual

Write the header for generics.

Implemented in verilog_writer, and VHDL_writer.

◆ write_port_decl_tail()

virtual void language_writer::write_port_decl_tail ( )

pure virtual

Write the tail for generics.

Implemented in verilog_writer, and VHDL_writer.

◆ write_port_declaration()

virtual void language_writer::write_port_declaration	(	const structural_objectRef &	cir,
		bool	first_port_analyzed
	)

pure virtual

Write the port declaration starting from a port object.

Parameters

cir	is the port to be written.

Implemented in verilog_writer, and VHDL_writer.

◆ write_present_state_update()

virtual void language_writer::write_present_state_update	(	const structural_objectRef	cir,
		const std::string &	reset_state,
		const std::string &	reset_port,
		const std::string &	clock_port,
		const std::string &	reset_type,
		bool	connect_present_next_state_signals
	)

pure virtual

write the present_state update process

Parameters

reset_state	is the reset state.
reset_port	is the reset port.
clock_port	is the clock port.
reset_type	when true the FSM will have an synchronous reset

Implemented in verilog_writer, and VHDL_writer.

◆ write_signal_declaration()

virtual void language_writer::write_signal_declaration ( const structural_objectRef & cir )

pure virtual

Write the declaration of a signal.

Parameters

cir	is the signal to be declared.

Implemented in verilog_writer, and VHDL_writer.

◆ write_state_declaration()

virtual void language_writer::write_state_declaration	(	const structural_objectRef &	cir,
		const std::list< std::string > &	list_of_states,
		const std::string &	reset_port,
		const std::string &	reset_state,
		bool	one_hot
	)

pure virtual

write the declaration of all the states of the finite state machine.

Parameters

list_of_states is the list of all the states.

Implemented in verilog_writer, and VHDL_writer.

◆ write_transition_output_functions()

virtual void language_writer::write_transition_output_functions	(	bool	single_proc,
		unsigned int	output_index,
		const structural_objectRef &	cir,
		const std::string &	reset_state,
		const std::string &	reset_port,
		const std::string &	start_port,
		const std::string &	clock_port,
		std::vector< std::string >::const_iterator &	first,
		std::vector< std::string >::const_iterator &	end,
		bool	is_yosys,
		const std::map< unsigned int, std::map< std::string, std::set< unsigned int >>> &	bypass_signals
	)

pure virtual

Write the transition and output functions.

Parameters

cir	is the component.
reset_port	is the reset port.
clock_port	is the clock port.
first	if the first iterator of the state table.
end	if the end iterator of the state table.
is_yosys	is true when the transition table is meant for YOSYS.

Implemented in verilog_writer, and VHDL_writer.

◆ write_vector_port_binding()

virtual void language_writer::write_vector_port_binding	(	const structural_objectRef &	port,
		bool	first_port_analyzed
	)

pure virtual

Implemented in verilog_writer, and VHDL_writer.

◆ WriteBuiltin()

virtual void language_writer::WriteBuiltin ( const structural_objectConstRef component )

pure virtual

Write a builtin component.

Parameters

component is the component to be printed

Implemented in verilog_writer, and VHDL_writer.

◆ WriteFile()

void language_writer::WriteFile ( const std::string & filename ) const

Write content to a file.

Parameters

std::stringg filename;

Definition at line 123 of file language_writer.cpp.

References indented_output_stream, and IndentedOutputStream::WriteFile().

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◆ WriteLicense()

COPYING3_SHORT_MACRO void language_writer::WriteLicense ( )

Write the license.

Definition at line 142 of file language_writer.cpp.

References symmetry::row, and write_comment().

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◆ WriteString()

const std::string language_writer::WriteString ( ) const

Dump the content of the write as a string.

Definition at line 118 of file language_writer.cpp.

References indented_output_stream, and IndentedOutputStream::WriteString().

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Field Documentation

◆ debug_level

int language_writer::debug_level

protected

debugging level of the class

Definition at line 114 of file language_writer.hpp.

Referenced by system_verilog_writer::system_verilog_writer(), VHDL_writer::type_converter_size(), verilog_writer::verilog_writer(), VHDL_writer::VHDL_writer(), VHDL_writer::write_module_parametrization(), verilog_writer::write_module_parametrization(), VHDL_writer::write_module_parametrization_decl(), verilog_writer::write_module_parametrization_decl(), VHDL_writer::write_port_binding(), verilog_writer::write_state_declaration(), VHDL_writer::write_transition_output_functions(), verilog_writer::write_transition_output_functions(), VHDL_writer::write_vector_port_binding(), verilog_writer::write_vector_port_binding(), and VHDL_writer::WriteBuiltin().

◆ indented_output_stream

const IndentedOutputStreamRef language_writer::indented_output_stream

protected

Represents the stream we are currently writing to.

Definition at line 102 of file language_writer.hpp.

◆ list_of_customized_gates

CustomOrderedSet<std::string> language_writer::list_of_customized_gates

protected

list of customized gates

Definition at line 108 of file language_writer.hpp.

◆ list_of_lib

CustomOrderedSet<std::string> language_writer::list_of_lib

protected

list of library imported (e.g., includes).

Definition at line 105 of file language_writer.hpp.

◆ parameters

const ParameterConstRef language_writer::parameters

protected

the set of input parameters

Definition at line 111 of file language_writer.hpp.

Referenced by system_verilog_writer::get_extension(), verilog_writer::get_extension(), VHDL_writer::get_extension(), system_verilog_writer::system_verilog_writer(), verilog_writer::verilog_writer(), VHDL_writer::VHDL_writer(), system_verilog_writer::write_NP_functionalities(), VHDL_writer::write_NP_functionalities(), verilog_writer::write_NP_functionalities(), VHDL_writer::write_present_state_update(), verilog_writer::write_present_state_update(), VHDL_writer::write_state_declaration(), verilog_writer::write_state_declaration(), and verilog_writer::write_transition_output_functions().

The documentation for this class was generated from the following files:

/workspace/src/design_flows/backend/ToHDL/language_writer.hpp
/workspace/src/design_flows/backend/ToHDL/language_writer.cpp

Public Member Functions

Static Public Member Functions

Protected Member Functions

Protected Attributes

Detailed Description

Constructor & Destructor Documentation

◆ language_writer()

◆ ~language_writer()

Member Function Documentation

◆ bitnumber()

◆ check_keyword()

◆ create_writer()

◆ encode_one_hot()

◆ get_extension()

◆ get_name()

◆ GetHDLReservedNames()

◆ has_output_prefix()

◆ type_converter()

◆ type_converter_size()

◆ write()

◆ write_assign()

◆ write_comment()

◆ write_component_declaration()

◆ write_header()

◆ write_io_signal_post_fix()

◆ write_io_signal_post_fix_vector()

◆ write_library_declaration()

◆ write_module_declaration()

◆ write_module_definition_begin()

◆ write_module_definition_end()

◆ write_module_instance_begin()

◆ write_module_instance_end()

◆ write_module_internal_declaration()

◆ write_module_parametrization()

◆ write_module_parametrization_decl()

◆ write_NP_functionalities()

◆ write_port_binding()

◆ write_port_decl_header()

◆ write_port_decl_tail()

◆ write_port_declaration()

◆ write_present_state_update()

◆ write_signal_declaration()

◆ write_state_declaration()

◆ write_transition_output_functions()

◆ write_vector_port_binding()

◆ WriteBuiltin()

◆ WriteFile()

◆ WriteLicense()

◆ WriteString()

Field Documentation

◆ debug_level

◆ indented_output_stream

◆ list_of_customized_gates

◆ list_of_lib

◆ parameters