PandA-2024.02
generate_taste_hdl_architecture.cpp
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40 #include "generate_taste_hdl_architecture.hpp"
41 
42 #include "config_PACKAGE_BUGREPORT.hpp"
43 #include "config_PACKAGE_NAME.hpp"
44 #include "config_PACKAGE_VERSION.hpp"
45 
46 #include "Parameter.hpp"
47 #include "aadl_information.hpp"
48 #include "behavioral_helper.hpp"
49 #include "call_graph_manager.hpp"
50 #include "fileIO.hpp"
51 #include "function_behavior.hpp"
52 #include "generic_device.hpp"
53 #include "hls.hpp"
54 #include "hls_device.hpp"
55 #include "hls_manager.hpp"
56 #include "language_writer.hpp"
57 #include "string_manipulation.hpp"
58 #include "structural_manager.hpp"
59 #include "tree_manager.hpp"
60 
61 GenerateTasteHDLArchitecture::GenerateTasteHDLArchitecture(const ParameterConstRef _parameters,
62  const HLS_managerRef _HLSMgr,
63  const DesignFlowManagerConstRef _design_flow_manager)
64  : HLS_step(_parameters, _HLSMgr, _design_flow_manager, HLSFlowStep_Type::GENERATE_TASTE_HDL_ARCHITECTURE)
65 {
66 }
67 
68 DesignFlowStep_Status GenerateTasteHDLArchitecture::Exec()
69 {
70  const auto TreeM = HLSMgr->get_tree_manager();
71  const technology_managerConstRef TM = HLSMgr->get_HLS_device()->get_technology_manager();
72  language_writerRef writer = language_writer::create_writer(HDLWriter_Language::VHDL, TM, parameters);
73  writer->write_comment(std::string("File automatically generated by: ") + PACKAGE_NAME +
74  " framework version=" + PACKAGE_VERSION + "\n");
75  writer->write_comment(std::string("Send any bug to: ") + PACKAGE_BUGREPORT + "\n");
76  writer->WriteLicense();
77 
78  writer->write_comment("Description : This file is based on LEON3 Demonstration design.\n");
79  writer->write_comment("It implements the different components of the architecture :\n");
80  writer->write_comment("Gailser reset generator, clock generator, clock pads and PCI pads.\n");
81  writer->write_comment("Gailser simple target PCI\n");
82  writer->write_comment("Gailser AHB controller\n");
83  writer->write_comment("Gailser APB bridge\n");
84  writer->write_comment("APB wrappers\n");
85  writer->write("\n");
86  writer->write("library ieee;\n");
87  writer->write("use ieee.std_logic_1164.all;\n");
88  writer->write("\n");
89  writer->write("library grlib, techmap;\n");
90  writer->write("use grlib.amba.all;\n");
91  writer->write("use grlib.stdlib.all;\n");
92  writer->write("use techmap.gencomp.all;\n");
93  writer->write("\n");
94  writer->write("library gaisler;\n");
95  writer->write("use gaisler.misc.all;\n");
96  writer->write("use gaisler.pci.all;\n");
97  writer->write("\n");
98  writer->write("use work.config.all;\n");
99  writer->write("\n");
100  writer->write("entity TASTE_hardware_architecture is\n");
101  writer->write(" generic (\n");
102  writer->write(" fabtech : integer := CFG_FABTECH;\n");
103  writer->write(" memtech : integer := CFG_MEMTECH;\n");
104  writer->write(" padtech : integer := CFG_PADTECH;\n");
105  writer->write(" clktech : integer := CFG_CLKTECH\n");
106  writer->write(" );\n");
107  writer->write(" port (\n");
108  writer->write(" resetn : in std_logic;\n");
109  writer->write(" clk : in std_logic;\n");
110  writer->write(" pllref : in std_logic;\n");
111  writer->write("\n");
112  writer->write(" pci_rst : inout std_logic;\n");
113  writer->write(" pci_clk : in std_logic;\n");
114  writer->write(" pci_gnt : in std_logic;\n");
115  writer->write(" pci_idsel : in std_logic;\n");
116  writer->write(" pci_lock : inout std_logic;\n");
117  writer->write(" pci_ad : inout std_logic_vector(31 downto 0);\n");
118  writer->write(" pci_cbe : inout std_logic_vector(3 downto 0);\n");
119  writer->write(" pci_frame : inout std_logic;\n");
120  writer->write(" pci_irdy : inout std_logic;\n");
121  writer->write(" pci_trdy : inout std_logic;\n");
122  writer->write(" pci_devsel : inout std_logic;\n");
123  writer->write(" pci_stop : inout std_logic;\n");
124  writer->write(" pci_perr : inout std_logic;\n");
125  writer->write(" pci_par : inout std_logic;\n");
126  writer->write(" pci_req : inout std_logic;\n");
127  writer->write(" pci_serr : inout std_logic;\n");
128  writer->write(" pci_host : in std_logic;\n");
129  writer->write(" pci_66 : in std_logic\n");
130  writer->write(" );\n");
131  writer->write("end;\n");
132  writer->write("\n");
133  writer->write("architecture rtl of TASTE_hardware_architecture is\n");
134  writer->write("\n");
135  for(const auto& top_function : HLSMgr->aadl_information->top_functions_names)
136  {
137  const auto function_node = TreeM->GetFunction(top_function);
138  const auto SM = HLSMgr->get_HLS(function_node->index)->top;
139  const auto circuit = SM->get_circ();
140  writer->write_component_declaration(circuit);
141  }
142 
143  writer->write("signal apbi : apb_slv_in_type;\n");
144  writer->write("signal apbo : apb_slv_out_vector := (others => apb_none);\n");
145  writer->write("signal ahbsi : ahb_slv_in_type;\n");
146  writer->write("signal ahbso : ahb_slv_out_vector := (others => ahbs_none);\n");
147  writer->write("signal ahbmi : ahb_mst_in_type;\n");
148  writer->write("signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);\n");
149  writer->write("\n");
150  writer->write("signal clkm, rstn, rstraw, pciclk, lclk, pci_lclk : std_logic;\n");
151  writer->write("signal cgi : clkgen_in_type;\n");
152  writer->write("signal cgo : clkgen_out_type;\n");
153  writer->write("\n");
154  writer->write("signal pcii : pci_in_type;\n");
155  writer->write("signal pcio : pci_out_type;\n");
156  writer->write("\n");
157  writer->write("constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz\n");
158  writer->write("\n");
159  size_t counter = 0;
160  for(const auto& top_function : HLSMgr->aadl_information->top_functions_names)
161  {
162  writer->write_comment(top_function + "\n");
163  writer->write("constant pconfig_" + STR(counter) + " : apb_config_type := (\n");
164  writer->write(" 0 => ahb_device_reg ( 16#ff#, 1, 0, 1, 0),\n");
165  writer->write(" 1 => apb_iobar(" + STR(counter) + ", " + STR(counter) + "));\n\n");
166  counter++;
167  }
168  writer->write("\n");
169  writer->write("begin\n");
170  writer->write("\n");
171  writer->write_comment("--------------------------------------------------------------------\n");
172  writer->write_comment("- Reset and Clock generation -------------------------------------\n");
173  writer->write_comment("--------------------------------------------------------------------\n");
174  writer->write("\n");
175  writer->write(" cgi.pllctrl <= \"00\"; cgi.pllrst <= rstraw;\n");
176  writer->write("\n");
177  writer->write(" pllref_pad : clkpad\n");
178  writer->write(" generic map (tech => padtech)\n");
179  writer->write(" port map (pllref, cgi.pllref);\n");
180  writer->write("\n");
181  writer->write(" clk_pad : clkpad\n");
182  writer->write(" generic map (tech => padtech)\n");
183  writer->write(" port map (clk, lclk);\n");
184  writer->write("\n");
185  writer->write(" pci_clk_pad : clkpad\n");
186  writer->write(" generic map (tech => padtech, level => pci33)\n");
187  writer->write(" port map (pci_clk, pci_lclk);\n");
188  writer->write("\n");
189  writer->write(" clkgen0 : clkgen\n");
190  writer->write(" generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0,\n");
191  writer->write(" 0, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)\n");
192  writer->write(" port map (lclk, pci_lclk, clkm, open, open, open, pciclk, cgi, cgo);\n");
193  writer->write("\n");
194  writer->write(" rst0 : rstgen\n");
195  writer->write(" port map (resetn, clkm, cgo.clklock, rstn, rstraw);\n");
196  writer->write("\n");
197  writer->write_comment("--------------------------------------------------------------------\n");
198  writer->write_comment("- AHB CONTROLLER --------------------------------------------------\n");
199  writer->write_comment("--------------------------------------------------------------------\n");
200  writer->write("\n");
201  writer->write(" ahb0 : ahbctrl\n");
202  writer->write(" generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,\n");
203  writer->write(" rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,\n");
204  writer->write(" ioen => 1,nahbm => 2, nahbs => 1)\n");
205  writer->write(" port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);\n");
206  writer->write("\n");
207  writer->write_comment("---------------------------------------------------------------------\n");
208  writer->write_comment("- PCI Simple Target-------------------------------------------------\n");
209  writer->write_comment("---------------------------------------------------------------------\n");
210  writer->write("\n");
211  writer->write(" pci0 : pci_target\n");
212  writer->write(" generic map (hindex => 0,device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)\n");
213  writer->write(" port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(0));\n");
214  writer->write("\n");
215  writer->write("\n");
216  writer->write(" pcipads0 : pcipads\n");
217  writer->write(" generic map (padtech => padtech)\n");
218  writer->write(" port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,\n");
219  writer->write(" pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,\n");
220  writer->write(" pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );\n");
221  writer->write("\n");
222  writer->write_comment("--------------------------------------------------------------------\n");
223  writer->write_comment("- APB Bridge -----------------------------------------------------\n");
224  writer->write_comment("--------------------------------------------------------------------\n");
225  writer->write("\n");
226  writer->write(" apb0 : apbctrl\n");
227  writer->write(" generic map (hindex => 0, haddr => CFG_APBADDR)\n");
228  writer->write(" port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo );\n");
229  writer->write("\n");
230  writer->write_comment("---------------------------------------------------------------------\n");
231  writer->write_comment("- Custom IP wrapper ------------------------------------------------\n");
232  writer->write_comment("---------------------------------------------------------------------\n");
233  writer->write("\n");
234  writer->write("\n");
235  counter = 0;
236  for(const auto& top_function : HLSMgr->aadl_information->top_functions_names)
237  {
238  writer->write(top_function + "_instance : " + top_function + "_taste_interface generic map(pindex => " +
239  STR(counter) + ", paddr => " + STR(counter) +
240  ") port map (clock => clkm, reset => rstn, apbi_psel => apbi.psel(" + STR(counter) +
241  "), apbi_penable => apbi.penable, apbi_pwrite => apbi.pwrite, apbi_pwdata => apbi.pwdata, "
242  "apbi_paddr => apbi.paddr, apbo_prdata => apbo(" +
243  STR(counter) + ").prdata);\n\n");
244  writer->write("apbo(" + STR(counter) + ").pconfig <= pconfig_" + STR(counter) + ";\n\n");
245  counter++;
246  }
247  writer->write("end;\n");
248  writer->WriteFile(GetPath("architecture_top.vhd"));
249  HLSMgr->hdl_files.push_back(GetPath("top.vhd"));
250  HLSMgr->hdl_files.push_back(GetPath("architecture_top.vhd"));
251 
253  language_writerRef config_writer = language_writer::create_writer(HDLWriter_Language::VHDL, TM, parameters);
254  config_writer->write_comment(std::string("File automatically generated by: ") + PACKAGE_NAME +
255  " framework version=" + PACKAGE_VERSION + "\n");
256  config_writer->write_comment(std::string("Send any bug to: ") + PACKAGE_BUGREPORT + "\n");
257  config_writer->WriteLicense();
258 
259  config_writer->write("library techmap;\n");
260  config_writer->write("use techmap.gencomp.all;\n");
261  config_writer->write("\n");
262  config_writer->write("library ieee;\n");
263  config_writer->write("use ieee.std_logic_1164.all;\n");
264  config_writer->write("\n");
265  config_writer->write("package config is\n");
266  config_writer->write(" -- Technology and synthesis options\n");
267  config_writer->write(" constant CFG_FABTECH : integer := virtex4;\n");
268  config_writer->write(" constant CFG_MEMTECH : integer := virtex4;\n");
269  config_writer->write(" constant CFG_PADTECH : integer := virtex4;\n");
270  config_writer->write(" -- Clock generator\n");
271  config_writer->write(" constant CFG_CLKTECH : integer := virtex4;\n");
272  config_writer->write("\n");
273  config_writer->write(" -- TASTE specific:\n");
274  config_writer->write(" -- If your Synthesis reports that you have to lessen the clock,\n");
275  config_writer->write(" -- (i.e. less than 100MHz) , you have to modify these two:\n");
276  config_writer->write(" -- (default value: 2x50/1 = 100MHz\n");
277  config_writer->write(" constant CFG_CLKMUL : integer := (2);\n");
278  config_writer->write(" constant CFG_CLKDIV : integer := (1);\n");
279  config_writer->write("\n");
280  config_writer->write("\n");
281  config_writer->write(" constant CFG_PCIDLL : integer := 0;\n");
282  config_writer->write(" constant CFG_PCISYSCLK: integer := 0;\n");
283  config_writer->write(" -- AMBA settings\n");
284  config_writer->write(" constant CFG_DEFMST : integer := (0);\n");
285  config_writer->write(" constant CFG_RROBIN : integer := 1;\n");
286  config_writer->write(" constant CFG_SPLIT : integer := 0;\n");
287  config_writer->write(" constant CFG_AHBIO : integer := 16#FFF#;\n");
288  config_writer->write(" constant CFG_APBADDR : integer := 16#800#;\n");
289  config_writer->write(" -- PCI interface\n");
290  config_writer->write(" constant CFG_PCI : integer := 1;\n");
291  config_writer->write(" constant CFG_PCIVID : integer := 16#1AC8#;\n");
292  config_writer->write(" constant CFG_PCIDID : integer := 16#0054#;\n");
293  config_writer->write("\n");
294  config_writer->write(" -- TASTE specific:\n");
295  config_writer->write(" -- types for byte arrays\n");
296  config_writer->write(" type octStr_16 is array (0 to 15) of std_logic_vector(7 downto 0);\n");
297  config_writer->write(" type octStr_24 is array (0 to 23) of std_logic_vector(7 downto 0);\n");
298  config_writer->write("end;\n");
299 
300  config_writer->WriteFile(GetPath("architecture_config.vhd"));
301  HLSMgr->hdl_files.push_back(GetPath("architecture_config.vhd"));
302 
303  return DesignFlowStep_Status::SUCCESS;
304 }
305 
306 bool GenerateTasteHDLArchitecture::HasToBeExecuted() const
307 {
308  return true;
309 }
310 
311 const CustomUnorderedSet<std::tuple<HLSFlowStep_Type, HLSFlowStepSpecializationConstRef, HLSFlowStep_Relationship>>
312 GenerateTasteHDLArchitecture::ComputeHLSRelationships(const DesignFlowStep::RelationshipType relationship_type) const
313 {
314  CustomUnorderedSet<std::tuple<HLSFlowStep_Type, HLSFlowStepSpecializationConstRef, HLSFlowStep_Relationship>> ret;
315  switch(relationship_type)
316  {
317  case DEPENDENCE_RELATIONSHIP:
318  {
319  ret.insert(std::make_tuple(parameters->getOption<HLSFlowStep_Type>(OPT_hls_flow),
320  HLSFlowStepSpecializationConstRef(), HLSFlowStep_Relationship::ALL_FUNCTIONS));
321  break;
322  }
323  case INVALIDATION_RELATIONSHIP:
324  {
325  break;
326  }
327  case PRECEDENCE_RELATIONSHIP:
328  {
329  break;
330  }
331  default:
332  THROW_UNREACHABLE("");
333  }
334  return ret;
335 }
HDLWriter_Language::VHDL
aadl_information.hpp
The information collected from aadl file.
HLS_step::HLSMgr
const HLS_managerRef HLSMgr
information about all the HLS synthesis
Definition: hls_step.hpp:205
hls_manager.hpp
Data structure representing the entire HLS information.
behavioral_helper.hpp
DesignFlowStep::RelationshipType
RelationshipType
The relationship type.
Definition: design_flow_step.hpp:135
DesignFlowStep::INVALIDATION_RELATIONSHIP
Source must be executed to satisfy target.
Definition: design_flow_step.hpp:138
language_writer::create_writer
static language_writerRef create_writer(HDLWriter_Language language, const technology_managerConstRef TM, const ParameterConstRef parameters)
Creates the specialization of the writer based on the desired language.
Definition: language_writer.cpp:87
DesignFlowStep_Status::SUCCESS
Step skipped.
GenerateTasteHDLArchitecture::GenerateTasteHDLArchitecture
GenerateTasteHDLArchitecture(const ParameterConstRef _parameters, const HLS_managerRef HLSMgr, const DesignFlowManagerConstRef design_flow_manager)
Constructor.
Definition: generate_taste_hdl_architecture.cpp:61
STR
#define STR(s)
Macro which performs a lexical_cast to a string.
Definition: string_manipulation.hpp:52
string_manipulation.hpp
Auxiliary methods for manipulating string.
THROW_UNREACHABLE
#define THROW_UNREACHABLE(str_expr)
helper function used to specify that some points should never be reached
Definition: exceptions.hpp:292
HLS_step
Definition: hls_step.hpp:198
HLSFlowStep_Type
HLSFlowStep_Type
Definition: hls_step.hpp:95
language_writer.hpp
This class writes different HDL based descriptions (VHDL, Verilog, SystemC) starting from a structura...
fileIO.hpp
utility function used to read files.
DesignFlowStep::parameters
const ParameterConstRef parameters
Set of input parameters.
Definition: design_flow_step.hpp:123
DesignFlowStep_Status
DesignFlowStep_Status
The status of a step.
Definition: design_flow_step.hpp:97
GetPath
std::string GetPath(std::filesystem::path path)
Definition: fileIO.hpp:140
HLSFlowStep_Relationship::ALL_FUNCTIONS
GenerateTasteHDLArchitecture::ComputeHLSRelationships
const CustomUnorderedSet< std::tuple< HLSFlowStep_Type, HLSFlowStepSpecializationConstRef, HLSFlowStep_Relationship > > ComputeHLSRelationships(const DesignFlowStep::RelationshipType relationship_type) const override
Return the set of analyses in relationship with this design step.
Definition: generate_taste_hdl_architecture.cpp:312
refcount
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
Parameter.hpp
this class is used to manage the command-line or XML options.
call_graph_manager.hpp
Wrapper to call graph.
structural_manager.hpp
Class implementation of the structural_manager.
counter
unsigned counter[N_THREADS]
Definition: data.c:3
generic_device.hpp
Generic device description.
generate_taste_hdl_architecture.hpp
Implementation of the class to generate the top HDL taste architecture.
hls.hpp
Data structure definition for high-level synthesis flow.
GenerateTasteHDLArchitecture::Exec
DesignFlowStep_Status Exec() override
Execute the step.
Definition: generate_taste_hdl_architecture.cpp:68
tree_manager.hpp
Class specification of the manager of the tree structures extracted from the raw file.
GenerateTasteHDLArchitecture::HasToBeExecuted
bool HasToBeExecuted() const override
Check if this step has actually to be executed.
Definition: generate_taste_hdl_architecture.cpp:306
hls_device.hpp
HLS specialization of generic_device.
function_behavior.hpp
A brief description of the C++ Header File.
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