verilog_writer.hpp

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/*
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 *
 *             ***********************************************
 *                              PandA Project
 *                     URL: http://panda.dei.polimi.it
 *                       Politecnico di Milano - DEIB
 *                        System Architectures Group
 *             ***********************************************
 *              Copyright (C) 2004-2024 Politecnico di Milano
 *
 *   This file is part of the PandA framework.
 *
 *   The PandA framework is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 3 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */
#ifndef VERILOG_WRITER_HPP
#define VERILOG_WRITER_HPP

#include "language_writer.hpp"

#include <list>
#include <map>
#include <set>
#include <string>
#include <vector>

class verilog_writer : public language_writer
{
 protected:
   static const std::map<std::string, std::string> builtin_to_verilog_keyword;

   static const std::set<std::string> keywords;

 public:
   static bool check_keyword_verilog(const std::string& word);

   std::string get_name() const override
   {
      return "verilog";
   }
   std::string get_extension() const override
   {
      return ".v";
   }
   void write_comment(const std::string& comment_string) override;
   std::string type_converter(structural_type_descriptorRef Type) override;
   std::string type_converter_size(const structural_objectRef& cir) override;

   std::string may_slice_string(const structural_objectRef& cir);

   void write_library_declaration(const structural_objectRef& cir) override;
   void write_module_declaration(const structural_objectRef& cir) override;
   void write_module_internal_declaration(const structural_objectRef& cir) override;
   void write_port_declaration(const structural_objectRef& cir, bool last_port_to_analyze) override;
   void write_component_declaration(const structural_objectRef& cir) override;
   void write_signal_declaration(const structural_objectRef& cir) override;
   void write_module_definition_begin(const structural_objectRef& cir) override;
   void write_module_instance_begin(const structural_objectRef& cir, const std::string& module_name,
                                    bool write_parametrization) override;

   void write_module_instance_end(const structural_objectRef& cir) override;
   void write_port_binding(const structural_objectRef& port, const structural_objectRef& object_bounded,
                           bool first_port_analyzed) override;
   void write_vector_port_binding(const structural_objectRef& port, bool first_port_analyzed) override;
   void write_module_definition_end(const structural_objectRef& cir) override;
   void write_io_signal_post_fix(const structural_objectRef& port, const structural_objectRef& sig) override;
   void write_io_signal_post_fix_vector(const structural_objectRef& port, const structural_objectRef& sig) override;
   void write_module_parametrization(const structural_objectRef& cir) override;
   void write_state_declaration(const structural_objectRef& cir, const std::list<std::string>& list_of_states,
                                const std::string& reset_port, const std::string& reset_state, bool one_hot) override;
   void write_present_state_update(const structural_objectRef cir, const std::string& reset_state,
                                   const std::string& reset_port, const std::string& clock_port,
                                   const std::string& reset_type, bool connect_present_next_state_signals) override;

   void write_transition_output_functions(
       bool single_proc, unsigned int output_index, const structural_objectRef& cir, const std::string& reset_state,
       const std::string& reset_port, const std::string& start_port, const std::string& clock_port,
       std::vector<std::string>::const_iterator& first, std::vector<std::string>::const_iterator& end, bool is_yosys,
       const std::map<unsigned int, std::map<std::string, std::set<unsigned int>>>& bypass_signals) override;

   void write_NP_functionalities(const structural_objectRef& cir) override;

   void write_port_decl_header() override;

   void write_port_decl_tail() override;

   void write_module_parametrization_decl(const structural_objectRef& cir) override;

   explicit verilog_writer(const ParameterConstRef parameters);

   ~verilog_writer() override;

   void write_assign(const std::string& op0, const std::string& op1) override;

   bool has_output_prefix() const override
   {
      return true;
   }

   bool check_keyword(const std::string& id) const override;

   void write_header() override;

   void WriteBuiltin(const structural_objectConstRef component) override;
};

#endif