PandA-2024.02
controller_creator_base_step.hpp
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44 #ifndef CONTROLLER_CREATOR_BASE_STEP_HPP
45 #define CONTROLLER_CREATOR_BASE_STEP_HPP
46 
48 #include "hls_function_step.hpp"
49 
51 #include "graph.hpp"
52 
54 #include <fstream>
55 
57 #include "custom_map.hpp"
58 #include "custom_set.hpp"
59 #include <tuple>
60 
62 #include "refcount.hpp"
63 
72 class xml_element;
74 
79 {
80  protected:
86  ComputeHLSRelationships(const DesignFlowStep::RelationshipType relationship_type) const override;
87 
88  public:
93  const DesignFlowManagerConstRef design_flow_manager,
95 
99  ~ControllerCreatorBaseStep() override;
100 
101  protected:
105  void Initialize() override;
106 
112 
119  std::map<generic_objRef, unsigned int> out_ports;
120 
125  std::map<vertex, unsigned int> cond_ports;
127  std::map<vertex, unsigned int> mu_ports;
128 
130  unsigned int out_num;
131 
133  unsigned int in_num;
134 
135  private:
141 
148 
154 
165 };
168 
169 #endif
const CustomUnorderedSet< std::tuple< HLSFlowStep_Type, HLSFlowStepSpecializationConstRef, HLSFlowStep_Relationship > > ComputeHLSRelationships(const DesignFlowStep::RelationshipType relationship_type) const override
Return the set of analyses in relationship with this design step.
const HLS_managerRef HLSMgr
information about all the HLS synthesis
Definition: hls_step.hpp:205
void Initialize() override
Initialize the step (i.e., like a constructor, but executed just before exec.
void add_clock_reset(structural_objectRef circuit, structural_managerRef SM)
Adds the clock and reset ports to a circuit.
virtual void add_common_ports(structural_objectRef circuit, structural_managerRef SM)
This member function adds the standard ports (clock, reset, done and command ones) to a circuit...
void add_done_port(structural_objectRef circuit, structural_managerRef SM)
Adds the done port to a circuit.
RelationshipType
The relationship type.
const unsigned int funId
identifier of the function to be processed (0 means that it is a global step)
Class specification of the graph structures.
This class manages the circuit structures.
void add_command_ports(structural_objectRef circuit, structural_managerRef SM)
Adds the command ports to a circuit.
ControllerCreatorBaseStep(const ParameterConstRef Param, const HLS_managerRef HLSMgr, unsigned int funId, const DesignFlowManagerConstRef design_flow_manager, const HLSFlowStep_Type hls_flow_step_type)
Constructor.
std::map< vertex, unsigned int > cond_ports
This is the same as in_ports except that the first element is of type vertex.
const HLSFlowStep_Type hls_flow_step_type
The type of this step.
Definition: hls_step.hpp:208
redefinition of map to manage ordered/unordered structures
~ControllerCreatorBaseStep() override
Destructor.
unsigned int in_num
Initialized after add_common_ports is called. It represents the current number of input ports...
unsigned int out_num
Initialized after add_common_ports is called. It represents the current number of output ports...
HLSFlowStep_Type
Definition: hls_step.hpp:95
redefinition of set to manage ordered/unordered structures
Generic class managing all resources into datapath.
Definition: generic_obj.hpp:66
const Wrefcount< const DesignFlowManager > design_flow_manager
The design flow manager.
std::map< generic_objRef, unsigned int > out_ports
This contains all the ports that go from the controller to the datapath, used to enable the registers...
void add_start_port(structural_objectRef circuit, structural_managerRef SM)
Adds the start port to a circuit.
Template definition of refcount.
Generic class managing controller creation algorithms.
Template borrowed from the ANTLR library by Terence Parr (http://www.jGuru.com - Software rights: htt...
Definition: refcount.hpp:94
REF_FORWARD_DECL(hls)
Data structure that contains all information about high level synthesis process.
Definition: hls.hpp:83
Superclass include.
Base object for all the structural objects.
std::map< vertex, unsigned int > mu_ports
This map put into relation fsm states and alldone multi_unbounded ports.

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