PandA-2024.02
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#include <TestbenchDUTModuleGenerator.hpp>
Public Member Functions | |
TestbenchDUTModuleGenerator (const HLS_managerRef &HLSMgr) | |
void | InternalExec (std::ostream &out, structural_objectRef mod, unsigned int function_id, vertex op_v, const HDLWriter_Language language, const std::vector< ModuleGenerator::parameter > &_p, const std::vector< ModuleGenerator::parameter > &_ports_in, const std::vector< ModuleGenerator::parameter > &_ports_out, const std::vector< ModuleGenerator::parameter > &_ports_inout) final |
Definition at line 48 of file TestbenchDUTModuleGenerator.hpp.
TestbenchDUTModuleGenerator::TestbenchDUTModuleGenerator | ( | const HLS_managerRef & | HLSMgr | ) |
Definition at line 59 of file TestbenchDUTModuleGenerator.cpp.
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final |
Definition at line 63 of file TestbenchDUTModuleGenerator.cpp.
References structural_manager::add_port(), verilog_writer::check_keyword_verilog(), CLOCK_PORT_NAME, DONE_PORT_NAME, GET_TYPE_SIZE, MINIMAL_INTERFACE_GENERATION, test_panda::parameters, port_vector_o_K, RESET_PORT_NAME, START_PORT_NAME, str, THROW_ASSERT, THROW_ERROR, THROW_UNREACHABLE, top(), U, VERILOG, and WB4_INTERFACE_GENERATION.