- s -

s : p_update_check , prng_rand_t
s_typeNames : structural_type_descriptor
same_data_size_accesses : memory
saodg : FunctionBehavior
satur_to_list : boost::dsatur_coloring_helper< VertexListGraph, ColorMap, size_type >
SC_builtin_scalar_type : tree_helper
SC_tmpl_class : tree_helper
scalar_to_scalar : Vectorize
scalar_to_vector : Vectorize
sch : OpVertexSchedSorter , ScheduleWriter
schedule : bloc , commutative_expr_restructuring , CondExprRestructuring , CSE , fanout_opt , MultipleEntryIfReduction , PhiOpt , RemoveEndingIf , simple_code_motion , UpdateSchedule
scheduling_constraints : HLS_constraints
scope : action_o , gimple_pragma , HWCallPathCalculator
scope_and_name_to_sig_info : vcd_parser
scp : glpk_solver
scpe : decl_node , gimple_node , type_node
screen_location : _brick , _entity
script_map : SynthesisTool
script_name : BackendStep , SynthesisTool
sdg : FunctionBehavior , topological_based_sorting_visitor< OutputIterator >
search_function : PragmaParser
second : mux_obj
selected_vcd_signals : Discrepancy
selector : cc_compatibility_graph_edge_selector< Graph > , cdfc_graph_edge_selector< Graph > , edge_cdfc_selector , edge_compatibility_selector , EdgeProperty , EdgeWriter , graph , mux_obj , SelectEdge< Graph > , UEdgeWriter , ugraph , weak_dominance
selectors : conn_binding
separator : xml_parameter_t
seqA : bench_args_t
seqB : bench_args_t
set_chain : dom_info< GraphObj >
set_child : dom_info< GraphObj >
set_size : dom_info< GraphObj >
setup_multiplier : AllocationInformation
setup_script : ToolManager
sg : FunctionBehavior
shape : DLTensor
shared_fun_scope : HWCallPathCalculator
shared_function_proxy : functions
shared_functions : functions
sharing_operations : SDCScheduling
sig_n : vcd_parser
sign : FloatFormat , RealRange , vcDouble::_FP_STRUCT_LAYOUT , vcFloat::_FP_STRUCT_LAYOUT
signal : commandport_obj
signal_type : signal_o
signals_ : signal_o
signature_to_vertex : DesignFlowGraphsCollection
signed_p : flopoco_wrapper
signed_var : BitLatticeManipulator
significand : RealRange
sim_tool : SimulationInformation
simd_loop_type : Vectorize
simple_functions : fun_dominator_allocation
simple_pipeline : function_decl , FunctionBehavior
simple_pointer_plus_expr : AllocationInformation
single_bool_test_cond_expr_units : AllocationInformation
single_one_delivered : buffer_state
singleValue : xml_parameter_t , xml_set_variable_t
sink : OpNode
size : dataset_t , field_decl , OctetStringAsnType , parm_decl , result_decl , SequenceOfAsnType , SetOfAsnType , structural_type_descriptor , TVMByteArray , type_node , var_decl
size_DEFAULT : structural_type_descriptor
size_parameter : port_o
skip : AadlFlexLexer , AsnFlexLexer
skipped_executions : DesignFlowManager
sl : multi_way_if , MultipleEntryIfReduction , PhiOpt , RemoveEndingIf
slack_time : module_binding_check< vertex_type > , slack_based_filtering
slot : aggr_init_expr
SM : generic_obj , HDL_manager , top_entity
small_normalized_resource_area : cdfc_module_binding
smt_ann : field_decl , parm_decl , result_decl , var_decl
soft_discr_list : vcd_utility
sol : bench_args_t
solverType : RangeAnalysis
source : ControlDepNode , Edge , UnaryOpNode
source1 : BinaryOpNode , TernaryOpNode
source2 : BinaryOpNode , TernaryOpNode
source3 : TernaryOpNode
source_bloc : tree_node_dup , tree_node_index_factory
source_name : Translator::LatexColumnFormat
source_tn : tree_node_dup , tree_node_index_factory
source_values : memory
sourceBb : StateInfo
sources : LoadOpNode , PhiOpNode
sp_back_edges : Loop
sp_var_end : vcd_trace_head
sp_var_it : vcd_trace_head
sparse_logic : conn_binding
spcs : template_decl
spec : Schedule , Scheduling
spec_flag : record_type
specialized : functional_unit_template , module
speculation : ASLAP , Scheduling
spt_vector_edges : port_swapping
src_filename : CBackendInformation
ssa_bb_versions : AllocationInformation
ssa_cond_exprs : AllocationInformation
ssa_id : DiscrepancyLog
ssa_name : DiscrepancyOpInfo
ssa_name_node_id : DiscrepancyOpInfo
ssa_plugin_name : CompilerWrapper::Compiler
ssa_plugin_obj : CompilerWrapper::Compiler
ssa_roots : AllocationInformation
ssa_to_skip : Discrepancy
ssa_to_skip_if_address : Discrepancy
stack : tree_manager
stage_period : time_info
stage_period_DEFAULT : time_info
stall_reg_table : reg_binding
start : weak_dominance
start_nodes : operations_cfg_computation
start_op : liveness
start_state_is_initial : vcd_trace_head
start_states : DiscrepancyOpInfo
start_vars : vcd_trace_head
startidx : thread_data
starting_cycles_to_ops : Schedule
starting_node : bench_args_t
starting_operations : StateInfo
starting_time : module_binding_check< vertex_type > , parametric_list_based , slack_based_filtering
starting_times : Schedule , StartingTimeSorter
state : vcd_trace_head
state_graph : last_intermediate_state , next_unique_state
state_id_to_vertex : StateTransitionGraphInfo
state_in_definitions : liveness
state_index : StateTransitionGraph_constructor
state_out_definitions : liveness
state_transition_graph : StateTransitionGraph_constructor
state_transition_graphs_collection : StateTransitionGraph_constructor , StateTransitionGraphManager
state_variables : FunctionBehavior
statements_list : BBNodeInfo
static_flag : function_decl , var_decl
static_static_flag : var_decl
status : DesignFlowStepInfo , MemoryInitializationWriterBase
std_functor : pointer_var_pp_functor
step : target_mem_ref461 , target_mem_ref
step_counter : DesignFlowManager
step_names : DesignFlowManager
steps : BackendFlow
STG : hls
STG_builder : StateTransitionGraphManager
stg_fun_id : DiscrepancyOpInfo
STG_graph : StateTransitionGraphManager
stmt_string : DiscrepancyLog
stop_iteration : RangeAnalysis
stop_transformation : RangeAnalysis
storage_index_double_map : StorageValueInformationPipeline
storage_index_map : StorageValueInformationFsm
storage_value_information : hls
str : gimple_asm , integer_type
strg : AadlParserNode , AsnParserNode , identifier_node , string_cst
strides : DLTensor
string_cst_map : string_cst_fix
string_to_CO : Translator::LatexColumnFormat
string_to_TF : Translator::LatexColumnFormat
string_to_TOF : Translator::LatexColumnFormat
struct_flag : record_type
structural_manager : structural_object
subgraph_vertices : SelectEdge< Graph >
subprogram_features : AadlParserData
subset : SelectVertex< Graph >
success_executions : DesignFlowManager
suffix : modelsimWrapper , VerilatorWrapper , VIVADO_xsim_wrapper
sum : bench_args_t
support : boost::maxclique_dsatur_coloring_helper< VertexListGraph, ColorMap, size_type, SET_container > , boost::select_vertex< SET_container > , cc_compatibility_graph_vertex_selector< Graph > , cdfc_graph_vertex_selector< Graph >
support_cfg : EdgeCWriter
support_set : liveness
supported_types : operation
swap_computed_table : mux_connection_binding
switch_map_size : Scheduling
switch_normalizing_map : Scheduling
symbol : target_mem_ref
symbol_name : memory_symbol
SymbolicSource : SigmaOpNode
sync_handle : TVMParallelGroupEnv
sync_ram_var_latency : AllocationInformation
synthesis_dependent : time_info
system_features : AadlParserData
system_flag : type_node
system_properties : AadlParserData
systemIncPath : CheckSystemType